[MIRParser] Avoid repeated map lookups (NFC) (#123561)

[CodeGen] Remove unused includes (NFC) (#115996)

Identified with misc-include-cleaner.

[GlobalISel] Import samesign flag (#114267)

Credits: https://github.com/llvm/llvm-project/pull/111419

Fixes icmp-flags.mir

First attempt: https://github.com/llvm/llvm-project/pull/113090

Re

[GlobalISel] Import samesign flag (#114267)

Credits: https://github.com/llvm/llvm-project/pull/111419

Fixes icmp-flags.mir

First attempt: https://github.com/llvm/llvm-project/pull/113090

Revert: https://github.com/llvm/llvm-project/pull/114256

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Revert "[GlobalISel] Import samesign flag" (#114256)

Reverts llvm/llvm-project#113090

[GlobalISel] Import samesign flag (#113090)

Credits: https://github.com/llvm/llvm-project/pull/111419

[AArch64][Libunwind] Add Support for FEAT_PAuthLR DWARF Instruction (#112171)

As part of FEAT_PAuthLR, a new DWARF Frame Instruction was introduced,
`DW_CFA_AARCH64_negate_ra_state_with_pc`. This i

[AArch64][Libunwind] Add Support for FEAT_PAuthLR DWARF Instruction (#112171)

As part of FEAT_PAuthLR, a new DWARF Frame Instruction was introduced,
`DW_CFA_AARCH64_negate_ra_state_with_pc`. This instructs Libunwind that
the PC has been used with the signing instruction. This change includes
three commits
- Libunwind support for the newly introduced DWARF Instruction
- CodeGen Support for the DWARF Instructions
- Reversing the changes made in #96377. Due to
`DW_CFA_AARCH64_negate_ra_state_with_pc`'s requirements to be placed
immediately after the signing instruction, this would mean the CFI
Instruction location was not consistent with the generated location when
not using FEAT_PAuthLR. The commit reverses the changes and makes the
location consistent across the different branch protection options.
While this does have a code size effect, this is a negligible one.

For the ABI information, see here:
https://github.com/ARM-software/abi-aa/blob/853286c7ab66048e4b819682ce17f567b77a0291/aadwarf64/aadwarf64.rst#id23

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[MIR] Add missing noteNewVirtualRegister callbacks (#111634)

The delegates' callback isn't invoked on parsing new virtual registers.

There are two places in the serialization where new virtual regi

[MIR] Add missing noteNewVirtualRegister callbacks (#111634)

The delegates' callback isn't invoked on parsing new virtual registers.

There are two places in the serialization where new virtual registers can be discovered: in register infos and in instructions.

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[MIR] Serialize virtual register flags (#110228)

[MIR] Serialize virtual register flags

This introduces target-specific vreg flag serialization. Flags are represented as `uint8_t` and the `TargetRe

[MIR] Serialize virtual register flags (#110228)

[MIR] Serialize virtual register flags

This introduces target-specific vreg flag serialization. Flags are represented as `uint8_t` and the `TargetRegisterInfo` override provides methods `getVRegFlagValue` to deserialize and `getVRegFlagsOfReg` to serialize.

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[NFC] Move intrinsic related functions to Intrinsic namespace (#110125)

Move static functions `Function::lookupIntrinsicID` and
`Function::isTargetIntrinsic` to Intrinsic namespace.

Reapply "Deprecate the `-fbasic-block-sections=labels` option." (#110039)

This reapplies commit 1911a50fae8a441b445eb835b98950710d28fc88 with a
minor fix in lld/ELF/LTO.cpp which sets Options.BBAdd

Reapply "Deprecate the `-fbasic-block-sections=labels` option." (#110039)

This reapplies commit 1911a50fae8a441b445eb835b98950710d28fc88 with a
minor fix in lld/ELF/LTO.cpp which sets Options.BBAddrMap when
`--lto-basic-block-sections=labels` is passed.

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Revert "Deprecate the `-fbasic-block-sections=labels` option. (#107494)"

This reverts commit 1911a50fae8a441b445eb835b98950710d28fc88.

Several bots are failing:

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Revert "Deprecate the `-fbasic-block-sections=labels` option. (#107494)"

This reverts commit 1911a50fae8a441b445eb835b98950710d28fc88.

Several bots are failing:

https://lab.llvm.org/buildbot/#/builders/190/builds/6519
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Deprecate the `-fbasic-block-sections=labels` option. (#107494)

This feature is supported via the newer option
`-fbasic-block-address-map`. Using the old option still works by
delegating to the ne

Deprecate the `-fbasic-block-sections=labels` option. (#107494)

This feature is supported via the newer option
`-fbasic-block-address-map`. Using the old option still works by
delegating to the newer option, while a warning is printed to show
deprecation.

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[LLVM] Use {} instead of std::nullopt to initialize empty ArrayRef (#109133)

It is almost always simpler to use {} instead of std::nullopt to
initialize an empty ArrayRef. This patch changes all oc

[LLVM] Use {} instead of std::nullopt to initialize empty ArrayRef (#109133)

It is almost always simpler to use {} instead of std::nullopt to
initialize an empty ArrayRef. This patch changes all occurrences I could
find in LLVM itself. In future the ArrayRef(std::nullopt_t) constructor
could be deprecated or removed.

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[llvm] Prefer StringRef::substr to StringRef::slice (NFC) (#105943)

S.substr(N) is simpler than S.slice(N, StringRef::npos) and
S.slice(N, S.size()). Also, substr is probably better recognizable
t

[llvm] Prefer StringRef::substr to StringRef::slice (NFC) (#105943)

S.substr(N) is simpler than S.slice(N, StringRef::npos) and
S.slice(N, S.size()). Also, substr is probably better recognizable
than slice thanks to std::string_view::substr.

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[MIR] Remove separate Size variable from parseMachineMemoryOperand. NFC (#101453)

Size is updated in sync with MemoryType. Instead of maintaining a
separate Size, use the size from MemoryType where

[MIR] Remove separate Size variable from parseMachineMemoryOperand. NFC (#101453)

Size is updated in sync with MemoryType. Instead of maintaining a
separate Size, use the size from MemoryType where needed.

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[RISCV][GlobalISel] Legalize Scalable Vector Loads and Stores (#84965)

This patch supports legalizing load and store instruction for scalable
vectors in RISCV

[MIR] Replace bespoke DIExpression parser

Resolve FIXME by using the LLParser implementation of parseDIExpression
from the MIParser.

[LLVM][MIR] Support parsing bfloat immediates in MIR parser (#96010)

Adds support in MIR parser for parsing bfloat immediates, and adds a
test for this.

[CodeGen] Add nneg and disjoint flags (#86650)

MachineInstr learned the new flags.

[GlobalISel] convergence control tokens and intrinsics (#67006)

[GlobalISel] Implement convergence control tokens and intrinsics in GMIR

In the IR translator, convert the LLVM token type to LLT::

[GlobalISel] convergence control tokens and intrinsics (#67006)

[GlobalISel] Implement convergence control tokens and intrinsics in GMIR

In the IR translator, convert the LLVM token type to LLT::token(), which is an
alias for the s0 type. These show up as implicit uses on convergent operations.

Differential Revision: https://reviews.llvm.org/D158147

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[AsmParser] Support non-consecutive global value numbers (#80013)

https://github.com/llvm/llvm-project/pull/78171 added support for
non-consecutive local value numbers. This extends the support for

[AsmParser] Support non-consecutive global value numbers (#80013)

https://github.com/llvm/llvm-project/pull/78171 added support for
non-consecutive local value numbers. This extends the support for global
value numbers (for globals and functions).

This means that it is now possible to delete an unnamed global
definition/declaration without breaking the IR.

This is a lot less common than unnamed local values, but it seems like
something we should support for consistency. (Unnamed globals are used a
lot in Rust though.)

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[llvm] Move CodeGenTypes library to its own directory (#79444)

Finally addresses https://reviews.llvm.org/D148769#4311232 :)

No behavior change.

[CodeGen] Split off PseudoSourceValueManager into separate header (NFC) (#73327)

Most users of PseudoSourceValue.h only need PseudoSourceValue, not the
PseudoSourceValueManager. However, this heade

[CodeGen] Split off PseudoSourceValueManager into separate header (NFC) (#73327)

Most users of PseudoSourceValue.h only need PseudoSourceValue, not the
PseudoSourceValueManager. However, this header pulls in some very
expensive dependencies like ValueMap.h, which is only used for the
manager.

Split off the manager into a separate header and include it only where
used.

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MachineVerifier: Reject extra non-register operands on instructions (#73758)

We were allowing extra immediate arguments, and only bothering to check
if registers were implicit or not.

Also conso

MachineVerifier: Reject extra non-register operands on instructions (#73758)

We were allowing extra immediate arguments, and only bothering to check
if registers were implicit or not.

Also consolidate extra operand checks in verifier, to make this
testable. We had 3 different places checking if you were trying to build
an instruction with more operands than allowed by the definition. We had
an assertion in addOperand, a direct check in the MIRParser to avoid the
assertion, and the machine verifier checks. Remove the assert and parser
check so the verifier can provide a consistent verification experience,
which will also handle instructions modified in place.

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[CodeGen][MIR] Support parsing of scalable vectors in MIR (#70893)

This patch builds on the support for vectors by adding ability to parse
scalable vectors in MIR and updates error messages to refl

[CodeGen][MIR] Support parsing of scalable vectors in MIR (#70893)

This patch builds on the support for vectors by adding ability to parse
scalable vectors in MIR and updates error messages to reflect that ability.

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