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Searched refs:setDesc (Results 1 – 25 of 106) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerBrUnless.cpp80 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
84 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
88 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
92 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
96 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
100 Def->setDesc(TII.get(GT_S_I32)); in runOnMachineFunction()
104 Def->setDesc(TII.get(LE_U_I32)); in runOnMachineFunction()
108 Def->setDesc(TII.get(LT_U_I32)); in runOnMachineFunction()
112 Def->setDesc(TII.get(GE_U_I32)); in runOnMachineFunction()
116 Def->setDesc(TII.get(GT_U_I32)); in runOnMachineFunction()
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H A DWebAssemblyRegStackify.cpp107 MI->setDesc(TII->get(WebAssembly::CONST_I32)); in convertImplicitDefToConstZero()
110 MI->setDesc(TII->get(WebAssembly::CONST_I64)); in convertImplicitDefToConstZero()
113 MI->setDesc(TII->get(WebAssembly::CONST_F32)); in convertImplicitDefToConstZero()
118 MI->setDesc(TII->get(WebAssembly::CONST_F64)); in convertImplicitDefToConstZero()
123 MI->setDesc(TII->get(WebAssembly::CONST_V128_I64x2)); in convertImplicitDefToConstZero()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp256 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
288 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
677 MIB->setDesc(TII.get(Opc)); in selectGlobal()
715 MIB->setDesc(TII.get(Opc)); in selectGlobal()
735 MIB->setDesc(TII.get(Opcodes.ADDrr)); in selectGlobal()
747 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); in selectGlobal()
750 MIB->setDesc(TII.get(Opcodes.ConstPoolLoad)); in selectGlobal()
756 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); in selectGlobal()
758 MIB->setDesc(TII.get(Opcodes.LDRLIT_ga_abs)); in selectGlobal()
807 MIB->setDesc(TII.get(ARM::MOVsr)); in selectShift()
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H A DThumb2InstrInfo.cpp559 MI.setDesc(TII.get(ARM::tMOVr)); in rewriteT2FrameIndex()
574 MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri)); in rewriteT2FrameIndex()
576 MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri)); in rewriteT2FrameIndex()
594 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
714 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
757 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp96 MI.setDesc(TII->get(LLIxL)); in shortenIIF()
101 MI.setDesc(TII->get(LLIxH)); in shortenIIF()
112 MI.setDesc(TII->get(Opcode)); in shortenOn0()
123 MI.setDesc(TII->get(Opcode)); in shortenOn01()
136 MI.setDesc(TII->get(Opcode)); in shortenOn001()
169 MI.setDesc(TII->get(Opcode)); in shortenFPConv()
196 MI.setDesc(TII->get(Opcode)); in shortenFusedFPOp()
365 MI.setDesc(TII->get(TwoOperandOpcode)); in processBlock()
H A DSystemZPostRewrite.cpp88 MBBI->setDesc(TII->get(LowOpcode)); in selectLOCRMux()
90 MBBI->setDesc(TII->get(HighOpcode)); in selectLOCRMux()
139 MBBI->setDesc(TII->get(LowOpcode)); in selectSELRMux()
141 MBBI->setDesc(TII->get(HighOpcode)); in selectSELRMux()
216 MI.setDesc(TII->get(TargetMemOpcode)); in selectMI()
H A DSystemZInstrInfo.cpp114 EarlierMI->setDesc(get(HighOpcode)); in splitMove()
115 MI->setDesc(get(LowOpcode)); in splitMove()
132 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
147 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode)); in expandRIPseudo()
164 MI.setDesc(get(LowOpcodeK)); in expandRIEPseudo()
172 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode)); in expandRIEPseudo()
186 MI.setDesc(get(Opcode)); in expandRXYPseudo()
196 MI.setDesc(get(Opcode)); in expandLOCPseudo()
241 MI->setDesc(get(SystemZ::LG)); in expandLoadStackGuard()
667 UseMI.setDesc(get(NewUseOpc)); in FoldImmediate()
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H A DSystemZElimCompare.cpp228 Branch->setDesc(TII->get(BRCT)); in convertToBRCT()
271 Branch->setDesc(TII->get(LATOpcode)); in convertToLoadAndTrap()
331 MI.setDesc(TII->get(ConvOpc)); in convertToLogical()
669 Branch->setDesc(TII->get(FusedOpcode)); in fuseCompareOperations()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp104 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
117 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
144 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
161 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp214 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B32)); in removeTerminatorBit()
219 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B64)); in removeTerminatorBit()
225 MI.setDesc(TII->get(AMDGPU::S_XOR_B64)); in removeTerminatorBit()
231 MI.setDesc(TII->get(AMDGPU::S_XOR_B32)); in removeTerminatorBit()
237 MI.setDesc(TII->get(AMDGPU::S_OR_B64)); in removeTerminatorBit()
243 MI.setDesc(TII->get(AMDGPU::S_OR_B32)); in removeTerminatorBit()
249 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B64)); in removeTerminatorBit()
255 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B32)); in removeTerminatorBit()
261 MI.setDesc(TII->get(AMDGPU::S_AND_B64)); in removeTerminatorBit()
267 MI.setDesc(TII->get(AMDGPU::S_AND_B32)); in removeTerminatorBit()
H A DSIShrinkInstructions.cpp245 MI.setDesc(TII->get(SOPKOpc)); in shrinkScalarCompare()
255 MI.setDesc(NewDesc); in shrinkScalarCompare()
361 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
474 MI.setDesc(TII->get(NewOpcode)); in shrinkMadFma()
533 MI.setDesc(TII->get(Opc)); in shrinkScalarLogicOp()
800 MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32)); in runOnMachineFunction()
841 MI.setDesc(TII->get(Opc)); in runOnMachineFunction()
861 MI.setDesc(TII->get(AMDGPU::S_MOVK_I32)); in runOnMachineFunction()
863 MI.setDesc(TII->get(AMDGPU::S_BREV_B32)); in runOnMachineFunction()
H A DSIFoldOperands.cpp277 MI->setDesc(TII->get(AMDGPU::IMPLICIT_DEF)); in updateOperand()
291 MI->setDesc(TII->get(NewMFMAOpc)); in updateOperand()
343 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
352 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
363 MI->setDesc(TII->get(ImmOpc)); in tryAddToFoldList()
635 UseMI->setDesc(TII->get(NewOpc)); in foldOperand()
679 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64)); in foldOperand()
693 UseMI->setDesc(TII->get(MovOp)); in foldOperand()
728 UseMI->setDesc(TII->get(AMDGPU::REG_SEQUENCE)); in foldOperand()
802 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64)); in foldOperand()
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H A DSIModeRegister.cpp181 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_t16_e64)); in getInstructionMode()
189 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
198 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_t16_e64)); in getInstructionMode()
206 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
H A DSIPreEmitPeephole.cpp196 MI.setDesc(TII->get(AMDGPU::S_BRANCH)); in optimizeVccBranch()
224 MI.setDesc(TII->get(AMDGPU::S_BRANCH)); in optimizeVccBranch()
234 MI.setDesc( in optimizeVccBranch()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86FixupGadgets.cpp566 MI.setDesc(TII->get(X86::MOV8rr)); in fixupWithoutExchange()
569 MI.setDesc(TII->get(X86::MOV16rr)); in fixupWithoutExchange()
572 MI.setDesc(TII->get(X86::MOV32rr)); in fixupWithoutExchange()
575 MI.setDesc(TII->get(X86::MOV64rr)); in fixupWithoutExchange()
578 MI.setDesc(TII->get(X86::MOV8rr_REV)); in fixupWithoutExchange()
581 MI.setDesc(TII->get(X86::MOV16rr_REV)); in fixupWithoutExchange()
584 MI.setDesc(TII->get(X86::MOV32rr_REV)); in fixupWithoutExchange()
587 MI.setDesc(TII->get(X86::MOV64rr_REV)); in fixupWithoutExchange()
H A DX86InstructionSelector.cpp340 I.setDesc(TII.get(X86::COPY)); in selectCopy()
575 I.setDesc(TII.get(NewOpc)); in selectLoadStoreOp()
611 I.setDesc(TII.get(NewOpc)); in selectFrameIndexOrGep()
663 I.setDesc(TII.get(NewOpc)); in selectGlobalValue()
715 I.setDesc(TII.get(NewOpc)); in selectConstant()
740 I.setDesc(TII.get(X86::COPY)); in selectTurnIntoCOPY()
806 I.setDesc(TII.get(X86::COPY)); in selectTruncOrPtrToInt()
915 I.setDesc(TII.get(X86::COPY)); in selectAnyext()
1166 I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr)); in selectExtract()
1168 I.setDesc(TII.get(X86::VEXTRACTF128rr)); in selectExtract()
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/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp251 MI.setDesc(get(VE::STrii)); in processSTQ()
271 MI.setDesc(get(VE::LDrii)); in processLDQ()
310 MI.setDesc(get(VE::STrii)); in processSTVM()
346 MI.setDesc(get(VE::LDrii)); in processLDVM()
408 MI.setDesc(get(VE::STrii)); in processSTVM512()
447 MI.setDesc(get(VE::LDrii)); in processLDVM512()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64CompressJumpTables.cpp147 MI.setDesc(TII->get(AArch64::JumpTableDest8)); in compressJumpTable()
153 MI.setDesc(TII->get(AArch64::JumpTableDest16)); in compressJumpTable()
/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp190 slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET)); in findDelayInstr()
394 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr) in combineRestoreADD()
433 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr) in combineRestoreOR()
470 RestoreMI->setDesc(TII->get(SP::RESTOREri)); in combineRestoreSETHIi()
H A DSparcRegisterInfo.cpp192 MI.setDesc(TII.get(SP::STDFri)); in eliminateFrameIndex()
205 MI.setDesc(TII.get(SP::LDDFri)); in eliminateFrameIndex()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCEarlyReturn.cpp93 MI->setDesc(TII->get(PPC::BCCLR)); in processBlock()
110 MI->setDesc( in processBlock()
H A DPPCInstrInfo.cpp2192 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) in PredicateInstruction()
2199 MI.setDesc(get(PPC::BCLR)); in PredicateInstruction()
2202 MI.setDesc(get(PPC::BCLRn)); in PredicateInstruction()
2205 MI.setDesc(get(PPC::BCCLR)); in PredicateInstruction()
2215 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) in PredicateInstruction()
2225 MI.setDesc(get(PPC::BC)); in PredicateInstruction()
2233 MI.setDesc(get(PPC::BCn)); in PredicateInstruction()
2241 MI.setDesc(get(PPC::BCC)); in PredicateInstruction()
2260 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) in PredicateInstruction()
2264 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) in PredicateInstruction()
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/openbsd-src/gnu/llvm/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp378 MIB->setDesc(get(Move)); in ExpandMOVX_RR()
454 MIB->setDesc(Desc); in ExpandMOVSZX_RM()
493 MIB->setDesc(get(M68k::MOV16cd)); in ExpandCCR()
496 MIB->setDesc(get(M68k::MOV16dc)); in ExpandCCR()
564 MIB->setDesc(Desc); in Expand2AddrUndef()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVStripWSuffix.cpp78 MI.setDesc(TII.get(Opc)); in runOnMachineFunction()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1024 I.setDesc(TII.get(AArch64::COPY)); in selectCopy()
1029 I.setDesc(TII.get(AArch64::COPY)); in selectCopy()
2061 I.setDesc(TII.get(AArch64::G_SITOF)); in preISelLower()
2063 I.setDesc(TII.get(AArch64::G_UITOF)); in preISelLower()
2101 I.setDesc(TII.get(TargetOpcode::G_ADD)); in convertPtrAddToAdd()
2115 I.setDesc(TII.get(TargetOpcode::G_SUB)); in convertPtrAddToAdd()
2253 I.setDesc(TII.get(TargetOpcode::COPY)); in earlySelect()
2413 I.setDesc(TII.get(TargetOpcode::PHI)); in select()
2483 I.setDesc(TII.get(AArch64::BR)); in select()
2497 I.setDesc(TII.get(AArch64::ADDXri)); in select()
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