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Searched refs:getSimpleVT (Results 1 – 25 of 73) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp849 switch (VT.getSimpleVT().SimpleTy) { in getLdStRegType()
909 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoad()
1040 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoadVector()
1090 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1097 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1117 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1124 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
1146 EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v2_ari_64, in tryLoadVector()
1154 EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_ari_64, in tryLoadVector()
1165 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector()
[all …]
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DValueTypes.h95 return getSimpleVT().changeVectorElementTypeToInteger(); in changeVectorElementTypeToInteger()
105 return getSimpleVT().changeVectorElementType(EltVT.getSimpleVT()); in changeVectorElementType()
118 return getSimpleVT().changeTypeToInteger(); in changeTypeToInteger()
288 MVT getSimpleVT() const { in getSimpleVT() function
H A DTargetLowering.h938 (unsigned)VT.getSimpleVT().SimpleTy < std::size(RegClassForVT)); in isTypeLegal()
939 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr; in isTypeLegal()
1119 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op]; in getOperationAction()
1300 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getLoadExtAction()
1301 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getLoadExtAction()
1325 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getTruncStoreAction()
1326 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getTruncStoreAction()
1364 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal || in isIndexedLoadLegal()
1365 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom); in isIndexedLoadLegal()
1378 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal || in isIndexedStoreLegal()
[all …]
H A DTargetCallingConv.h215 VT = vt.getSimpleVT(); in InputArg()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp247 MVT VT = RealVT.getSimpleVT(); in getRegForValue()
251 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); in getRegForValue()
310 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant()
393 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN); in getRegForGEPIndex()
396 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN); in getRegForGEPIndex()
473 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, CI->getZExtValue(), in selectBinaryOp()
474 VT.getSimpleVT()); in selectBinaryOp()
505 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm, in selectBinaryOp()
506 VT.getSimpleVT()); in selectBinaryOp()
520 Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVVPISelLowering.cpp61 auto Packing = getTypePacking(LegalVecVT.getSimpleVT()); in lowerToVVP()
153 Packing, DataVT.getVectorElementType().getSimpleVT()); in lowerVVP_LOAD_STORE()
181 MVT DataVT = getIdiomaticVectorType(Op.getNode())->getSimpleVT(); in splitPackedLoadStore()
268 getLegalVectorType(Packing, DataVT.getVectorElementType().getSimpleVT()); in lowerVVP_GATHER_SCATTER()
314 MVT DataVT = getIdiomaticVectorType(Op.getNode())->getSimpleVT(); in legalizeInternalLoadStoreOp()
410 MVT IdiomVT = getIdiomaticVectorType(Op.getNode())->getSimpleVT(); in legalizePackedAVL()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp531 LoadConversionTbl, ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost()
554 DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost()
566 DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost()
583 SrcTy.getSimpleVT(), DstTy.getSimpleVT())) in getCastInstrCost()
594 SrcTy.getSimpleVT(), DstTy.getSimpleVT())) in getCastInstrCost()
620 DstTy.getSimpleVT(), in getCastInstrCost()
621 SrcTy.getSimpleVT())) { in getCastInstrCost()
731 DstTy.getSimpleVT(), in getCastInstrCost()
732 SrcTy.getSimpleVT())) in getCastInstrCost()
761 DstTy.getSimpleVT(), in getCastInstrCost()
[all …]
H A DARMFastISel.cpp629 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
676 VT = evt.getSimpleVT(); in isTypeLegal()
1342 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp()
1537 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP()
1779 MVT VT = FPVT.getSimpleVT(); in SelectBinaryFPOp()
2127 MVT RVVT = RVEVT.getSimpleVT(); in SelectRet()
2192 return ARMMaterializeGV(GV, LCREVT.getSimpleVT()); in getLibcallReg()
2762 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIntExt()
2763 MVT DestVT = DestEVT.getSimpleVT(); in SelectIntExt()
3048 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
/openbsd-src/gnu/llvm/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp309 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
332 MVT VT = LD->getMemoryVT().getSimpleVT(); in tryIndexedLoad()
361 MVT VT = LD->getMemoryVT().getSimpleVT(); in tryIndexedBinOp()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp86 switch (LoadedVT.getSimpleVT().SimpleTy) { in INITIALIZE_PASS()
482 switch (StoredVT.getSimpleVT().SimpleTy) { in SelectIndexedStore()
703 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectExtractSubvector()
707 [[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT(); in SelectExtractSubvector()
796 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectVAlign()
859 MVT OpTy = Op.getValueType().getSimpleVT(); in SelectTypecast()
866 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectP2D()
874 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectD2P()
883 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectV2Q()
885 MVT OpTy = N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy; in SelectV2Q()
[all …]
H A DHexagonISelLowering.h418 return Op.getValueType().getSimpleVT(); in ty()
421 return { Ops.first.getValueType().getSimpleVT(), in ty()
422 Ops.second.getValueType().getSimpleVT() }; in ty()
H A DHexagonSubtarget.cpp192 MVT ElemTy = VecTy.getSimpleVT().getVectorElementType(); in isHVXVectorType()
238 MVT ElemTy = Ty.getVectorElementType().getSimpleVT(); in isTypeForHVX()
H A DHexagonISelDAGToDAGHVX.cpp678 : InpNode(Inp), InpTy(Inp->getValueType(0).getSimpleVT()) {} in ResultStack()
1189 MVT OpTy = Op.getValueType().getSimpleVT(); in materialize()
1840 MVT LegalTy = Lower.getTypeToTransformTo(Ctx, ElemTy).getSimpleVT(); in scalarizeShuffle()
2545 MVT ResTy = N->getValueType(0).getSimpleVT(); in selectExtractSubvector()
2549 [[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT(); in selectExtractSubvector()
2566 MVT ResTy = N->getValueType(0).getSimpleVT(); in selectShuffle()
2647 MVT Ty = N->getValueType(0).getSimpleVT(); in selectRor()
H A DHexagonISelLowering.cpp640 Subtarget.isHVXVectorType(VT.getSimpleVT()); in getPostIndexedAddressParts()
2140 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32; in isTruncateFree()
2160 MVT ResTy = ResVT.getSimpleVT(), SrcTy = SrcVT.getSimpleVT(); in isExtractSubvectorCheap()
3081 MVT MemTy = LN->getMemoryVT().getSimpleVT(); in LowerLoad()
3137 MVT StoreTy = SN->getMemoryVT().getSimpleVT(); in LowerStore()
3770 MVT SVT = VT.getSimpleVT(); in allowsMemoryAccess()
3780 MVT SVT = VT.getSimpleVT(); in allowsMisalignedMemoryAccesses()
/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp116 MVT VT = cast<MemSDNode>(Op)->getMemoryVT().getSimpleVT(); in SelectAddr()
133 MVT VT = LD->getMemoryVT().getSimpleVT(); in selectIndexedLoad()
372 MVT VT = LD->getMemoryVT().getSimpleVT(); in select()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp448 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
596 VT = evt.getSimpleVT(); in isTypeLegal()
1365 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
1734 MVT RVVT = RVEVT.getSimpleVT(); in selectRet()
1813 MVT SrcVT = SrcEVT.getSimpleVT(); in selectIntExt()
1814 MVT DestVT = DestEVT.getSimpleVT(); in selectIntExt()
1914 MVT DestVT = DestEVT.getSimpleVT(); in selectDivRem()
1975 MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT(); in selectShift()
2091 MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT(); in getRegEnsuringSimpleIntegerWidening()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86FastISel.cpp296 VT = evt.getSimpleVT(); in isTypeLegal()
491 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
663 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
702 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); in X86FastEmitExtend()
1259 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); in X86SelectRet()
1357 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode()
1380 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode()
1583 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, in X86SelectZExt()
1627 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::SIGN_EXTEND, in X86SelectSExt()
2435 MVT DstVT = TLI.getValueType(DL, I->getType()).getSimpleVT(); in X86SelectIntToFP()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp321 TLI->getAsmOperandValueType(DL, OpTy, true).getSimpleVT(); in lowerInlineAsm()
331 TLI->getAsmOperandValueType(DL, Call.getType()).getSimpleVT(); in lowerInlineAsm()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp274 VT = Evt.getSimpleVT(); in isTypeLegal()
824 MVT SrcVT = SrcEVT.getSimpleVT(); in PPCEmitCmp()
1076 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP()
1753 MVT RVVT = RVEVT.getSimpleVT(); in SelectRet()
1917 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIntExt()
1918 MVT DestVT = DestEVT.getSimpleVT(); in SelectIntExt()
2253 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp963 MVT SVT = VT.getSimpleVT(); in getTypeConversion()
1052 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); in getTypeConversion()
1075 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); in getTypeConversion()
1569 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown()
2233 MVT LoadMVT = LoadVT.getSimpleVT(); in isLoadBitCastBeneficial()
2238 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()) in isLoadBitCastBeneficial()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp472 MTy.getSimpleVT())) in getIntrinsicInstrCost()
2078 DstTy.getSimpleVT(), in getCastInstrCost()
2079 SrcTy.getSimpleVT())) in getCastInstrCost()
2109 FP16Tbl, ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost()
2314 const auto *Entry = CostTableLookup(DivTbl, ISD, VT.getSimpleVT()); in getArithmeticInstrCost()
2475 SelCondTy.getSimpleVT(), in getCmpSelInstrCost()
2476 SelValTy.getSimpleVT())) in getCmpSelInstrCost()
3125 CostTableLookup(ShuffleTbl, TTI::SK_Splice, PromotedVT.getSimpleVT()); in getSpliceCost()
H A DAArch64FastISel.cpp540 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
991 VT = evt.getSimpleVT(); in isTypeLegal()
1477 MVT VT = EVT.getSimpleVT(); in emitCmp()
2880 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed); in selectIntToFP()
2939 MVT VT = ArgVT.getSimpleVT().SimpleTy; in fastLowerArguments()
3860 MVT RVVT = RVEVT.getSimpleVT(); in selectRet()
3911 MVT SrcVT = SrcEVT.getSimpleVT(); in selectTrunc()
3912 MVT DestVT = DestEVT.getSimpleVT(); in selectTrunc()
4568 MVT DestVT = DestEVT.getSimpleVT(); in selectRem()
4917 IdxN = emitIntExt(IdxVT.getSimpleVT(), IdxN, PtrVT, /*isZExt=*/false); in getRegForGEPIndex()
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp82 FuncInfo->addLocal(ValueVT.getSimpleVT()); in getLocalForStackObject()
H A DWebAssemblyFastISel.cpp121 return VT.isSimple() ? VT.getSimpleVT().SimpleTy in getSimpleType()
1171 Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(), in selectBitCast()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp522 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments()
525 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()

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