Home
last modified time | relevance | path

Searched refs:ZeroReg (Results 1 – 25 of 26) sorted by relevance

12

/openbsd-src/gnu/llvm/llvm/tools/llvm-exegesis/lib/Mips/
H A DTarget.cpp74 unsigned ZeroReg; in loadImmediate() local
77 ZeroReg = Mips::ZERO; in loadImmediate()
82 ZeroReg = Mips::ZERO_64; in loadImmediate()
91 .addReg(ZeroReg) in loadImmediate()
104 .addReg(ZeroReg) in loadImmediate()
123 .addReg(ZeroReg) in loadImmediate()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp114 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
116 ZeroReg); in runOnMachineFunction()
122 .addReg(ZeroReg) in runOnMachineFunction()
H A DX86FrameLowering.cpp937 ZeroReg = InProlog ? X86::RCX in emitStackProbeInlineWindowsCoreCLR64() local
997 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
998 .addReg(ZeroReg, RegState::Undef) in emitStackProbeInlineWindowsCoreCLR64()
999 .addReg(ZeroReg, RegState::Undef); in emitStackProbeInlineWindowsCoreCLR64()
1006 .addReg(ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DRelocation.txt56 Register ZeroReg, RegisterOperand GPROpnd> {
59 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
H A DMipsSEInstrInfo.cpp87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
182 if (ZeroReg) in copyPhysReg()
183 MIB.addReg(ZeroReg); in copyPhysReg()
H A DMipsSEISelDAGToDAG.cpp85 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
93 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
99 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
122 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
H A DMipsAsmPrinter.cpp140 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
141 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); in emitPseudoIndirectBranch()
H A DMipsInstrInfo.td3198 Register ZeroReg, RegisterOperand GPROpnd> {
3206 (Addiu ZeroReg, tglobaladdr:$in)>;
3208 (Addiu ZeroReg, tblockaddress:$in)>;
3210 (Addiu ZeroReg, tjumptable:$in)>;
3212 (Addiu ZeroReg, tconstpool:$in)>;
3214 (Addiu ZeroReg, tglobaltlsaddr:$in)>;
3216 (Addiu ZeroReg, texternalsym:$in)>;
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp550 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
551 putConstant(I, ZeroReg, 0); in selectCmp()
556 ZeroReg)) in selectCmp()
562 RHSReg, ZeroReg)) in selectCmp()
H A DARMFastISel.cpp1476 unsigned ZeroReg = fastMaterializeConstant(Zero); in SelectCmp() local
1479 .addReg(ZeroReg).addImm(1) in SelectCmp()
/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp900 SDValue ZeroReg = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8); in LowerINLINEASM() local
901 if (Op.getOperand(Op.getNumOperands() - 1) == ZeroReg || in LowerINLINEASM()
902 Op.getOperand(Op.getNumOperands() - 2) == ZeroReg) { in LowerINLINEASM()
930 Ops.push_back(ZeroReg); in LowerINLINEASM()
1872 Register ZeroReg = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift() local
1873 BuildMI(*BB, MI, dl, TII.get(AVR::COPY), ZeroReg) in insertMultibyteShift()
1897 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), LowByte).addReg(ZeroReg); in insertMultibyteShift()
1915 Regs[I] = std::pair(ZeroReg, 0); in insertMultibyteShift()
1949 ExtByte = ZeroReg; in insertMultibyteShift()
1991 Regs[Regs.size() - 1] = std::pair(ZeroReg, 0); in insertMultibyteShift()
[all …]
H A DAVRExpandPseudoInsts.cpp436 Register ZeroReg = MI.getOperand(2).getReg(); in expand() local
460 .addReg(ZeroReg); in expand()
1342 Register ZeroReg = MI.getOperand(2).getReg(); in expand() local
1361 .addReg(ZeroReg); in expand()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3457 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple() argument
3472 MIB.addReg(ZeroReg); in copyGPRRegTuple()
4902 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
4921 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
4935 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
4936 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
5076 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, in getMaddPatterns()
5078 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) { in getMaddPatterns()
5935 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
5940 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
[all …]
H A DAArch64ExpandPseudoInsts.cpp76 unsigned ExtendImm, unsigned ZeroReg,
190 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
223 BuildMI(LoadCmpBB, MIMD, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
H A DAArch64InstrInfo.h174 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
H A DAArch64ISelDAGToDAG.cpp3449 unsigned ZeroReg; in tryShiftAmountMod() local
3453 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
3457 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
3460 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
3469 unsigned ZeroReg; in tryShiftAmountMod() local
3473 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
3477 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
3480 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
H A DAArch64FastISel.cpp380 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt() local
383 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
4889 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv() local
4892 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg, in selectSDiv()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h892 int64_t ZeroReg = MatchTable[CurrentIdx++]; in executeMatchTable() local
896 OutMIs[NewInsnID].addReg(ZeroReg); in executeMatchTable()
902 << OpIdx << ", " << ZeroReg << ")\n"); in executeMatchTable()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2730 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); in loadImmediate() local
2750 SrcReg = ZeroReg; in loadImmediate()
2772 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2796 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2825 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
4231 unsigned ZeroReg; in expandDivRem() local
4236 ZeroReg = Mips::ZERO_64; in expandDivRem()
4240 ZeroReg = Mips::ZERO; in expandDivRem()
4264 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4271 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/SPIRV/
H A DSPIRVInstructionSelector.cpp1095 Register ZeroReg = buildZerosVal(ResType, I); in selectSelect() local
1106 .addUse(ZeroReg) in selectSelect()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2114 MCRegister ZeroReg; in onlyFoldImmediate() local
2117 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2119 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in onlyFoldImmediate()
2125 UseMI.getOperand(UseIdx).setReg(ZeroReg); in onlyFoldImmediate()
H A DPPCISelLowering.cpp11744 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitPartwordAtomicBinary() local
11811 if (ptrA != ZeroReg) { in EmitPartwordAtomicBinary()
11856 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
11899 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
12777 Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitInstrWithCustomInserter() local
12809 if (ptrA != ZeroReg) { in EmitInstrWithCustomInserter()
12866 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
12890 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
H A DPPCISelDAGToDAG.cpp6108 SDValue ZeroReg = in Select() local
6131 Subtarget->isLittleEndian() ? PPC::LVSR : PPC::LVSL, dl, Type, ZeroReg, in Select()
6136 {ZeroReg, N->getOperand(1), N->getOperand(0)}); in Select()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1912 Register ZeroReg; in applyCombineUnmergeZExtToZExt() local
1914 if (!ZeroReg) in applyCombineUnmergeZExtToZExt()
1915 ZeroReg = Builder.buildConstant(Dst0Ty, 0).getReg(0); in applyCombineUnmergeZExtToZExt()
1916 replaceRegWith(MRI, MI.getOperand(Idx).getReg(), ZeroReg); in applyCombineUnmergeZExtToZExt()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp7720 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion() local
7722 ZeroReg, 0); in convertNonUniformLoopRegion()
7723 HeaderPHIBuilder.addReg(ZeroReg); in convertNonUniformLoopRegion()

12