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Searched refs:TrueReg (Results 1 – 18 of 18) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp652 Register TrueReg = in simplifyCode() local
654 if (!TrueReg.isVirtual()) in simplifyCode()
656 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
716 Register TrueReg = in simplifyCode() local
718 if (!TrueReg.isVirtual()) in simplifyCode()
720 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
H A DPPCInstrInfo.cpp1530 Register DstReg, Register TrueReg, in canInsertSelect() argument
1549 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
1574 ArrayRef<MachineOperand> Cond, Register TrueReg, in insertSelect() argument
1582 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
1634 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1635 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
3223 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
3230 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3232 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3234 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
H A DPPCInstrInfo.h556 ArrayRef<MachineOperand> Cond, Register TrueReg,
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp787 auto TrueReg = MIB.getReg(2); in selectSelect() local
789 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) && in selectSelect()
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
794 .addUse(TrueReg) in selectSelect()
H A DARMBaseInstrInfo.cpp2369 MachineOperand TrueReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
2372 const TargetRegisterClass *TrueClass = MRI.getRegClass(TrueReg.getReg()); in optimizeSelect()
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp918 Register TrueReg = getRegForValue(Select->getTrueValue()); in selectSelect() local
919 if (TrueReg == 0) in selectSelect()
927 std::swap(TrueReg, FalseReg); in selectSelect()
965 .addReg(TrueReg) in selectSelect()
H A DWebAssemblyISelLowering.cpp478 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
484 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
518 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute); in LowerFPToInt()
522 .addReg(TrueReg) in LowerFPToInt()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp539 Register DstReg, Register TrueReg, in canInsertSelect() argument
552 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
575 Register TrueReg, in insertSelect() argument
595 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
597 TrueReg = TReg; in insertSelect()
609 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
H A DSystemZInstrInfo.h244 ArrayRef<MachineOperand> Cond, Register TrueReg,
H A DSystemZISelLowering.cpp7561 Register TrueReg = MI->getOperand(1).getReg(); in createPHIsForSelects() local
7568 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
7570 if (RegRewriteTable.find(TrueReg) != RegRewriteTable.end()) in createPHIsForSelects()
7571 TrueReg = RegRewriteTable[TrueReg].first; in createPHIsForSelects()
7578 .addReg(TrueReg).addMBB(TrueMBB) in createPHIsForSelects()
7582 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h313 Register TrueReg, Register FalseReg, int &CondCycles,
319 Register TrueReg, Register FalseReg) const override;
324 Register TrueReg, Register FalseReg) const;
H A DSIInstrInfo.cpp1133 Register TrueReg, in insertVectorSelect() argument
1149 .addReg(TrueReg) in insertVectorSelect()
1164 .addReg(TrueReg) in insertVectorSelect()
1178 .addReg(TrueReg) in insertVectorSelect()
1192 .addReg(TrueReg) in insertVectorSelect()
1204 .addReg(TrueReg) in insertVectorSelect()
1224 .addReg(TrueReg) in insertVectorSelect()
1242 .addReg(TrueReg) in insertVectorSelect()
2850 Register DstReg, Register TrueReg, in canInsertSelect() argument
2857 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg); in canInsertSelect()
[all …]
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h903 Register TrueReg, Register FalseReg, in canInsertSelect() argument
927 Register TrueReg, Register FalseReg) const { in insertSelect() argument
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrInfo.h361 ArrayRef<MachineOperand> Cond, Register TrueReg,
H A DX86InstrInfo.cpp3357 Register DstReg, Register TrueReg, in canInsertSelect() argument
3372 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
3395 ArrayRef<MachineOperand> Cond, Register TrueReg, in insertSelect() argument
3405 .addReg(TrueReg) in insertSelect()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h232 ArrayRef<MachineOperand> Cond, Register TrueReg,
H A DAArch64InstrInfo.cpp607 Register DstReg, Register TrueReg, in canInsertSelect() argument
614 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
634 if (canFoldIntoCSel(MRI, TrueReg)) in canInsertSelect()
658 Register TrueReg, Register FalseReg) const { in insertSelect() argument
761 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg); in insertSelect()
766 TrueReg = FalseReg; in insertSelect()
780 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
785 .addReg(TrueReg) in insertSelect()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp5858 Register TrueReg = Sel.getTrueReg(); in matchSelectToLogical() local
5861 auto *TrueDef = getDefIgnoringCopies(TrueReg, MRI); in matchSelectToLogical()
5865 const LLT OpTy = MRI.getType(TrueReg); in matchSelectToLogical()
5874 if (Cond == TrueReg || (MaybeCstTrue && MaybeCstTrue->isOne())) { in matchSelectToLogical()
5886 MIB.buildAnd(DstReg, Cond, TrueReg); in matchSelectToLogical()
5894 MIB.buildOr(DstReg, MIB.buildNot(OpTy, Cond), TrueReg); in matchSelectToLogical()