| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVRedundantCopyElimination.cpp | 108 Register TargetReg = Cond[1].getReg(); in optimizeBlock() local
109 if (!TargetReg) in optimizeBlock()
124 TargetReg == DefReg) { in optimizeBlock()
136 if (MI->modifiesRegister(TargetReg, TRI)) in optimizeBlock()
147 assert(CondBr->getOperand(0).getReg() == TargetReg && "Unexpected register"); in optimizeBlock()
151 CondBr->clearRegisterKills(TargetReg, TRI); in optimizeBlock()
154 if (!MBB.isLiveIn(TargetReg)) in optimizeBlock()
155 MBB.addLiveIn(TargetReg); in optimizeBlock()
159 MMI.clearRegisterKills(TargetReg, TRI); in optimizeBlock()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 186 unsigned TargetReg = Inst.getOperand(1).getReg(); in emitInstruction() local
187 emitMask(TargetReg, IndirectBranchMaskReg, STI); in emitInstruction()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 992 unsigned TargetReg; in tracePredStateThroughIndirectBranches() local
1023 TargetReg = TI.getOperand(0).getReg(); in tracePredStateThroughIndirectBranches()
1043 TargetAddrSSA.AddAvailableValue(&MBB, TargetReg); in tracePredStateThroughIndirectBranches()
1110 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1115 TII->get(X86::MOV64ri32), TargetReg) in tracePredStateThroughIndirectBranches()
1123 TargetReg) in tracePredStateThroughIndirectBranches()
1135 TargetAddrSSA.AddAvailableValue(Pred, TargetReg); in tracePredStateThroughIndirectBranches()
1143 Register TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB); in tracePredStateThroughIndirectBranches() local
1154 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
1173 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
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| H A D | X86ExpandPseudo.cpp | 229 auto TargetReg = STI->getTargetTriple().isOSWindows() ? X86::RCX : X86::RDI; in expandCALL_RVMARKER() local
231 .addReg(TargetReg, RegState::Define) in expandCALL_RVMARKER()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 169 Register TargetReg) { in buildGitPtr() argument
174 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr()
175 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
180 .addReg(TargetReg, RegState::ImplicitDefine); in buildGitPtr()
183 BuildMI(MBB, I, DL, GetPC64, TargetReg); in buildGitPtr()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 896 Register TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
904 .addReg(TargetReg) in expandEhReturn()
907 .addReg(TargetReg) in expandEhReturn()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 3074 Register TargetReg = MI.getOperand(0).getReg(); in expandVSXMemPseudo() local
3076 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
3077 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
3161 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
3162 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
3183 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
3184 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 212 const SmallSet<Register, 2> &TargetReg,
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3635 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectBrJT() local
3640 {TargetReg, ScratchReg}, {JTAddr, Index}) in selectBrJT()
3643 MIB.buildInstr(AArch64::BR, {}, {TargetReg}); in selectBrJT()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2841 Register TargetReg, Register InsertReg, in buildBitFieldInsert() argument
2843 LLT TargetTy = B.getMRI()->getType(TargetReg); in buildBitFieldInsert()
2857 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); in buildBitFieldInsert()
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