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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMPredicates.td9 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
11 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
12 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
14 def NoV5T : Predicate<"!Subtarget->hasV5TOps()">;
15 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
17 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
19 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
20 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
23 def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">,
26 def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">,
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H A DARMMachineFunctionInfo.cpp17 const ARMSubtarget *Subtarget) { in GetBranchTargetEnforcement() argument
18 if (!Subtarget->isMClass() || !Subtarget->hasV7Ops()) in GetBranchTargetEnforcement()
64 const ARMSubtarget *Subtarget) in ARMFunctionInfo() argument
65 : isThumb(Subtarget->isThumb()), hasThumb2(Subtarget->hasThumb2()), in ARMFunctionInfo()
68 BranchTargetEnforcement(GetBranchTargetEnforcement(F, Subtarget)) { in ARMFunctionInfo()
69 if (Subtarget->isMClass() && Subtarget->hasV7Ops()) in ARMFunctionInfo()
H A DARMSelectionDAGInfo.cpp41 const ARMSubtarget &Subtarget = in EmitSpecializedLibcall() local
43 const ARMTargetLowering *TLI = Subtarget.getTargetLowering(); in EmitSpecializedLibcall()
142 static bool shouldGenerateInlineTPLoop(const ARMSubtarget &Subtarget, in shouldGenerateInlineTPLoop() argument
162 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold() && in shouldGenerateInlineTPLoop()
164 Subtarget.getMaxMemcpyTPInlineSizeThreshold()) in shouldGenerateInlineTPLoop()
173 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemcpy() local
177 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemcpy()
178 shouldGenerateInlineTPLoop(Subtarget, DAG, ConstantSize, Alignment, true)) in EmitTargetCodeForMemcpy()
192 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemcpy()
203 const unsigned MaxLoadsInLDM = Subtarget.isThumb1Only() ? 4 : 6; in EmitTargetCodeForMemcpy()
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H A DARMISelLowering.cpp485 : TargetLowering(TM), Subtarget(&STI) { in ARMTargetLowering()
486 RegInfo = Subtarget->getRegisterInfo(); in ARMTargetLowering()
487 Itins = Subtarget->getInstrItineraryData(); in ARMTargetLowering()
492 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() && in ARMTargetLowering()
493 !Subtarget->isTargetWatchOS() && !Subtarget->isTargetDriverKit()) { in ARMTargetLowering()
501 if (Subtarget->isTargetMachO()) { in ARMTargetLowering()
503 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() && in ARMTargetLowering()
504 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) { in ARMTargetLowering()
580 if (Subtarget->isAAPCS_ABI() && in ARMTargetLowering()
581 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() || in ARMTargetLowering()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp94 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>(); in getCalleeSavedRegs() local
97 if (Subtarget.hasMips64()) in getCalleeSavedRegs()
98 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList in getCalleeSavedRegs()
101 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList in getCalleeSavedRegs()
105 if (Subtarget.isSingleFloat()) in getCalleeSavedRegs()
108 if (Subtarget.isABI_N64()) in getCalleeSavedRegs()
111 if (Subtarget.isABI_N32()) in getCalleeSavedRegs()
114 if (Subtarget.isFP64bit()) in getCalleeSavedRegs()
117 if (Subtarget.isFPXX()) in getCalleeSavedRegs()
126 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); in getCallPreservedMask() local
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H A DMipsISelLowering.cpp105 return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32 in getRegisterTypeForCallingConv()
113 return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64); in getNumRegistersForCallingConv()
289 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { in MipsTargetLowering()
296 if (Subtarget.hasMips32r6()) in MipsTargetLowering()
351 if (Subtarget.isGP64bit()) { in MipsTargetLowering()
366 if (!Subtarget.isGP64bit()) { in MipsTargetLowering()
373 if (Subtarget.isGP64bit()) in MipsTargetLowering()
399 if (Subtarget.hasCnMips()) { in MipsTargetLowering()
413 if (!Subtarget.hasMips32r2()) in MipsTargetLowering()
416 if (!Subtarget.hasMips64r2()) in MipsTargetLowering()
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCLowerMASSVEntries.cpp52 static StringRef getCPUSuffix(const PPCSubtarget *Subtarget);
54 const PPCSubtarget *Subtarget);
57 const PPCSubtarget *Subtarget);
73 StringRef PPCLowerMASSVEntries::getCPUSuffix(const PPCSubtarget *Subtarget) { in getCPUSuffix() argument
75 if (!Subtarget) in getCPUSuffix()
78 if (Subtarget->isAIXABI() && Subtarget->hasP10Vector()) in getCPUSuffix()
80 if (Subtarget->hasP9Vector()) in getCPUSuffix()
82 if (Subtarget->hasP8Vector()) in getCPUSuffix()
84 if (Subtarget->isAIXABI()) in getCPUSuffix()
96 const PPCSubtarget *Subtarget) { in createMASSVFuncName() argument
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H A DPPCRegisterInfo.cpp186 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); in getCalleeSavedRegs() local
188 if (!TM.isPPC64() && Subtarget.isAIXABI()) in getCalleeSavedRegs()
190 if (Subtarget.hasVSX()) { in getCalleeSavedRegs()
191 if (Subtarget.pairedVectorMemops()) in getCalleeSavedRegs()
193 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) in getCalleeSavedRegs()
197 if (Subtarget.hasAltivec()) { in getCalleeSavedRegs()
198 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) in getCalleeSavedRegs()
213 !Subtarget.isUsingPCRelativeCalls(); in getCalleeSavedRegs()
217 if (Subtarget.isAIXABI()) in getCalleeSavedRegs()
220 if (Subtarget.pairedVectorMemops()) in getCalleeSavedRegs()
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H A DPPCFrameLowering.cpp86 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), in PPCFrameLowering()
87 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), in PPCFrameLowering()
88 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), in PPCFrameLowering()
89 LinkageSize(computeLinkageSize(Subtarget)), in PPCFrameLowering()
90 BasePointerSaveOffset(computeBasePointerSaveOffset(Subtarget)), in PPCFrameLowering()
91 CRSaveOffset(computeCRSaveOffset(Subtarget)) {} in PPCFrameLowering()
232 if (Subtarget.is64BitELFABI()) { in getCalleeSavedSpillSlots()
237 if (Subtarget.is32BitELFABI()) { in getCalleeSavedSpillSlots()
242 assert(Subtarget.isAIXABI() && "Unexpected ABI."); in getCalleeSavedSpillSlots()
244 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
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H A DPPCISelLowering.cpp156 : TargetLowering(TM), Subtarget(STI) { in PPCTargetLowering()
163 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering()
172 if (!Subtarget.hasEFPU2()) in PPCTargetLowering()
197 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
227 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
243 if (Subtarget.useCRBits()) { in PPCTargetLowering()
246 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
320 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
355 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
360 if (Subtarget.hasVSX()) { in PPCTargetLowering()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td26 // Subtarget Features (device properties)
744 // Subtarget Features (options and debugging)
1438 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1442 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1443 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1447 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1448 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1449 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1453 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1454 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td16 def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
25 : Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
33 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
40 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
48 def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
56 def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
63 def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
70 def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
78 def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
86 def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
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H A DRISCVISelLowering.cpp70 : TargetLowering(TM), Subtarget(STI) { in RISCVTargetLowering()
72 if (Subtarget.isRV32E()) in RISCVTargetLowering()
75 RISCVABI::ABI ABI = Subtarget.getTargetABI(); in RISCVTargetLowering()
79 !Subtarget.hasStdExtF()) { in RISCVTargetLowering()
83 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
85 !Subtarget.hasStdExtD()) { in RISCVTargetLowering()
89 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
104 MVT XLenVT = Subtarget.getXLenVT(); in RISCVTargetLowering()
109 if (Subtarget.hasStdExtZfhOrZfhmin()) in RISCVTargetLowering()
111 if (Subtarget.hasStdExtF()) in RISCVTargetLowering()
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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp52 const X86Subtarget &Subtarget = in EmitTargetCodeForMemset() local
70 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemset()
89 if (Subtarget.is64Bit() && Alignment > Align(8)) { // QWORD aligned in EmitTargetCodeForMemset()
122 bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in EmitTargetCodeForMemset()
154 static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepmovs() argument
157 const bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in emitRepmovs()
176 static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepmovsB() argument
179 return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, in emitRepmovsB()
184 static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget, in getOptimalRepmovsType() argument
196 return Subtarget.is64Bit() ? MVT::i64 : MVT::i32; in getOptimalRepmovsType()
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H A DX86ISelLowering.cpp109 : TargetLowering(TM), Subtarget(STI) { in X86TargetLowering()
110 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87(); in X86TargetLowering()
123 if (Subtarget.isAtom()) in X86TargetLowering()
125 else if (Subtarget.is64Bit()) in X86TargetLowering()
129 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in X86TargetLowering()
134 if (Subtarget.hasSlowDivide32()) in X86TargetLowering()
136 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit()) in X86TargetLowering()
141 if (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()) { in X86TargetLowering()
160 if (Subtarget.getTargetTriple().isOSMSVCRT()) { in X86TargetLowering()
170 if (!Subtarget.canUseCMPXCHG8B()) in X86TargetLowering()
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H A DX86FastISel.cpp50 const X86Subtarget *Subtarget; member in __anon57bb29530111::X86FastISel
56 Subtarget = &funcInfo.MF->getSubtarget<X86Subtarget>(); in X86FastISel()
130 return Subtarget->getInstrInfo(); in getInstrInfo()
150 return (VT == MVT::f64 && Subtarget->hasSSE2()) || in isScalarFPTypeInSSEReg()
151 (VT == MVT::f32 && Subtarget->hasSSE1()) || VT == MVT::f16; in isScalarFPTypeInSSEReg()
299 if (VT == MVT::f64 && !Subtarget->hasSSE2()) in isTypeLegal()
301 if (VT == MVT::f32 && !Subtarget->hasSSE1()) in isTypeLegal()
319 bool HasSSE1 = Subtarget->hasSSE1(); in X86FastEmitLoad()
320 bool HasSSE2 = Subtarget->hasSSE2(); in X86FastEmitLoad()
321 bool HasSSE41 = Subtarget->hasSSE41(); in X86FastEmitLoad()
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H A DX86LoadValueInjectionRetHardening.cpp63 const X86Subtarget *Subtarget = &MF.getSubtarget<X86Subtarget>(); in runOnMachineFunction() local
64 if (!Subtarget->useLVIControlFlowIntegrity() || !Subtarget->is64Bit()) in runOnMachineFunction()
73 const X86RegisterInfo *TRI = Subtarget->getRegisterInfo(); in runOnMachineFunction()
74 const X86InstrInfo *TII = Subtarget->getInstrInfo(); in runOnMachineFunction()
H A DX86RegisterInfo.cpp123 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); in getLargestLegalSuperClass() local
132 if (!Subtarget.hasAVX512() && in getLargestLegalSuperClass()
139 if (!Subtarget.hasVLX() && in getLargestLegalSuperClass()
146 if (Subtarget.hasVLX() && in getLargestLegalSuperClass()
153 if (Subtarget.hasAVX512() && in getLargestLegalSuperClass()
179 const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>(); in getPointerRegClass() local
183 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
199 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
204 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
208 if (Subtarget.isTarget64BitLP64()) in getPointerRegClass()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRMCInstLower.cpp27 const AVRSubtarget &Subtarget) const { in lowerSymbolOperand()
46 AVRMCExpr::create(Subtarget.hasEIJMPCALL() ? AVRMCExpr::VK_AVR_LO8_GS in lowerSymbolOperand()
55 AVRMCExpr::create(Subtarget.hasEIJMPCALL() ? AVRMCExpr::VK_AVR_HI8_GS in lowerSymbolOperand()
70 auto &Subtarget = MI.getParent()->getParent()->getSubtarget<AVRSubtarget>(); in lowerInstruction() local
91 lowerSymbolOperand(MO, Printer.getSymbol(MO.getGlobal()), Subtarget); in lowerInstruction()
95 MO, Printer.GetExternalSymbolSymbol(MO.getSymbolName()), Subtarget); in lowerInstruction()
105 MO, Printer.GetBlockAddressSymbol(MO.getBlockAddress()), Subtarget); in lowerInstruction()
109 Subtarget); in lowerInstruction()
113 Subtarget); in lowerInstruction()
/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp28 const CSKYSubtarget *Subtarget; member in __anon54c25e280111::CSKYDAGToDAGISel
38 Subtarget = &MF.getSubtarget<CSKYSubtarget>(); in runOnMachineFunction()
84 Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF); in INITIALIZE_PASS()
94 ReplaceNode(N, CurDAG->getMachineNode(Subtarget->hasE2() ? CSKY::ADDI32 in INITIALIZE_PASS()
283 if (!Subtarget->hasFPUv2DoubleFloat()) in selectBITCAST_TO_LOHI()
308 Subtarget->has2E3() ? CSKY::CLRC32 : CSKY::CLRC16, Dl, Type1); in selectAddCarry()
310 Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1}, in selectAddCarry()
314 Subtarget->has2E3() ? CSKY::SETC32 : CSKY::SETC16, Dl, Type1); in selectAddCarry()
316 Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1}, in selectAddCarry()
319 NewNode = CurDAG->getMachineNode(Subtarget->has2E3() ? CSKY::ADDC32 in selectAddCarry()
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H A DCSKY.td24 def HasFPUv2_SF : Predicate<"Subtarget->hasFPUv2SingleFloat()">,
31 def HasFPUv2_DF : Predicate<"Subtarget->hasFPUv2DoubleFloat()">,
37 def HasFdivdu : Predicate<"Subtarget->hasFdivdu()">,
44 def HasFPUv3_HI : Predicate<"Subtarget->hasFPUv3HalfWord()">,
51 def HasFPUv3_HF : Predicate<"Subtarget->hasFPUv3HalfFloat()">,
58 def HasFPUv3_SF : Predicate<"Subtarget->hasFPUv3SingleFloat()">,
65 def HasFPUv3_DF : Predicate<"Subtarget->hasFPUv3DoubleFloat()">,
71 def iHasFLOATE1 : Predicate<"Subtarget->hasFLOATE1()">,
77 def iHasFLOAT1E2 : Predicate<"Subtarget->hasFLOAT1E2()">,
83 def iHasFLOAT1E3 : Predicate<"Subtarget->hasFLOAT1E3()">,
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/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp56 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getReservedRegs() local
67 if (!Subtarget.is64Bit()) in getReservedRegs()
82 if (ReserveAppRegisters || !Subtarget.is64Bit()) in getReservedRegs()
90 if (!Subtarget.isV9()) { in getReservedRegs()
107 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getPointerRegClass() local
108 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getPointerRegClass()
173 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in eliminateFrameIndex() local
182 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { in eliminateFrameIndex()
184 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
196 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArch.td24 : Predicate<"Subtarget->is64Bit()">,
28 : Predicate<"!Subtarget->is64Bit()">,
40 : Predicate<"Subtarget->hasBasicF()">,
50 : Predicate<"Subtarget->hasBasicD()">,
59 : Predicate<"Subtarget->hasExtLSX()">,
69 : Predicate<"Subtarget->hasExtLASX()">,
78 : Predicate<"Subtarget->hasExtLVZ()">,
87 : Predicate<"Subtarget->hasExtLBT()">,
96 : Predicate<"Subtarget->hasLaGlobalWithPcrel()">,
105 : Predicate<"Subtarget->hasLaGlobalWithAbs()">,
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H A DLoongArchISelLowering.cpp44 : TargetLowering(TM), Subtarget(STI) { in LoongArchTargetLowering()
46 MVT GRLenVT = Subtarget.getGRLenVT(); in LoongArchTargetLowering()
49 if (Subtarget.hasBasicF()) in LoongArchTargetLowering()
51 if (Subtarget.hasBasicD()) in LoongArchTargetLowering()
78 if (Subtarget.is64Bit()) in LoongArchTargetLowering()
86 if (Subtarget.is64Bit()) { in LoongArchTargetLowering()
101 if (Subtarget.hasBasicF() && !Subtarget.hasBasicD()) in LoongArchTargetLowering()
103 if (Subtarget.hasBasicF()) in LoongArchTargetLowering()
105 if (Subtarget.hasBasicD()) in LoongArchTargetLowering()
113 if (Subtarget.is64Bit()) { in LoongArchTargetLowering()
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/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp79 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getRegAllocationHints() local
80 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in getRegAllocationHints()
192 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
193 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_SaveList in getCalleeSavedRegs()
199 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
203 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList in getCalleeSavedRegs()
215 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
216 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_RegMask in getCallPreservedMask()
223 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
227 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask in getCallPreservedMask()
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