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Searched refs:SrcVT (Results 1 – 25 of 48) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp167 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
824 MVT SrcVT = SrcEVT.getSimpleVT(); in PPCEmitCmp() local
826 if (SrcVT == MVT::i1 && Subtarget->useCRBits()) in PPCEmitCmp()
840 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || in PPCEmitCmp()
841 SrcVT == MVT::i8 || SrcVT == MVT::i1) { in PPCEmitCmp()
867 switch (SrcVT.SimpleTy) { in PPCEmitCmp()
932 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
957 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in SelectFPExt() local
960 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in SelectFPExt()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp183 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
184 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
187 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
189 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
190 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
192 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
991 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPExt() local
994 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1070 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPTrunc() local
1073 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
[all …]
H A DMipsMSAInstrInfo.td3606 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3608 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3609 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3663 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3666 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3667 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3671 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3674 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3675 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3679 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp197 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
232 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
257 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
260 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
263 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
1184 MVT SrcVT = RetVT; in emitAddSub() local
1210 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1299 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
2836 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); in selectFPToInt() local
2837 if (SrcVT == MVT::f128 || SrcVT == MVT::f16) in selectFPToInt()
[all …]
H A DAArch64ISelLowering.cpp3867 EVT SrcVT = SrcVal.getValueType(); in LowerFP_ROUND() local
3869 if (useSVEForFixedLengthVectorVT(SrcVT, in LowerFP_ROUND()
3873 if (SrcVT != MVT::f128) { in LowerFP_ROUND()
3875 if (useSVEForFixedLengthVectorVT(SrcVT)) in LowerFP_ROUND()
4012 EVT SrcVT = SrcVal.getValueType(); in LowerVectorFP_TO_INT_SAT() local
4016 uint64_t SrcElementWidth = SrcVT.getScalarSizeInBits(); in LowerVectorFP_TO_INT_SAT()
4028 EVT SrcElementVT = SrcVT.getVectorElementType(); in LowerVectorFP_TO_INT_SAT()
4033 MVT F32VT = MVT::getVectorVT(MVT::f32, SrcVT.getVectorNumElements()); in LowerVectorFP_TO_INT_SAT()
4035 SrcVT = F32VT; in LowerVectorFP_TO_INT_SAT()
4055 EVT IntVT = SrcVT.changeVectorElementTypeToInteger(); in LowerVectorFP_TO_INT_SAT()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1046 EVT SrcVT = Src.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
1047 int NumSrcElements = SrcVT.getVectorNumElements(); in ExpandANY_EXTEND_VECTOR_INREG()
1051 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()
1052 assert((VT.getSizeInBits() % SrcVT.getScalarSizeInBits()) == 0 && in ExpandANY_EXTEND_VECTOR_INREG()
1054 NumSrcElements = VT.getSizeInBits() / SrcVT.getScalarSizeInBits(); in ExpandANY_EXTEND_VECTOR_INREG()
1055 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(), in ExpandANY_EXTEND_VECTOR_INREG()
1057 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandANY_EXTEND_VECTOR_INREG()
1073 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask)); in ExpandANY_EXTEND_VECTOR_INREG()
1080 EVT SrcVT = Src.getValueType(); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1090 unsigned SrcEltWidth = SrcVT.getScalarSizeInBits(); in ExpandSIGN_EXTEND_VECTOR_INREG()
[all …]
H A DTargetLowering.cpp675 EVT SrcVT = Src.getValueType(); in SimplifyMultipleUseDemandedBits() local
677 if (SrcVT == DstVT) in SimplifyMultipleUseDemandedBits()
680 unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits(); in SimplifyMultipleUseDemandedBits()
687 if (SrcVT.isVector() && (NumDstEltBits % NumSrcEltBits) == 0) { in SimplifyMultipleUseDemandedBits()
689 unsigned NumSrcElts = SrcVT.getVectorNumElements(); in SimplifyMultipleUseDemandedBits()
712 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyMultipleUseDemandedBits()
825 EVT SrcVT = Src.getValueType(); in SimplifyMultipleUseDemandedBits() local
828 DstVT.getSizeInBits() == SrcVT.getSizeInBits() && in SimplifyMultipleUseDemandedBits()
829 DemandedBits.getActiveBits() <= SrcVT.getScalarSizeInBits()) { in SimplifyMultipleUseDemandedBits()
2239 EVT SrcVT = Src.getValueType(); in SimplifyDemandedBits() local
[all …]
H A DLegalizeDAG.cpp725 EVT SrcVT = LD->getMemoryVT(); in LegalizeLoadOps() local
726 TypeSize SrcWidth = SrcVT.getSizeInBits(); in LegalizeLoadOps()
730 if (SrcWidth != SrcVT.getStoreSizeInBits() && in LegalizeLoadOps()
738 (SrcVT != MVT::i1 || in LegalizeLoadOps()
743 unsigned NewWidth = SrcVT.getStoreSizeInBits(); in LegalizeLoadOps()
763 Result, DAG.getValueType(SrcVT)); in LegalizeLoadOps()
768 DAG.getValueType(SrcVT)); in LegalizeLoadOps()
774 assert(!SrcVT.isVector() && "Unsupported extload!"); in LegalizeLoadOps()
851 SrcVT.getSimpleVT())) { in LegalizeLoadOps()
879 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
[all …]
H A DFastISel.cpp1379 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectCast() local
1382 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1392 if (!TLI.isTypeLegal(SrcVT)) in selectCast()
1400 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1417 MVT SrcVT = SrcEVT.getSimpleVT(); in selectBitCast() local
1424 if (SrcVT == DstVT) { in selectBitCast()
1430 Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); in selectBitCast()
1784 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectOperator() local
1786 if (DstVT.bitsGT(SrcVT)) in selectOperator()
1788 if (DstVT.bitsLT(SrcVT)) in selectOperator()
H A DLegalizeFloatTypes.cpp948 static RTLIB::Libcall findFPToIntLibcall(EVT SrcVT, EVT RetVT, EVT &Promoted, in findFPToIntLibcall() argument
957 LC = Signed ? RTLIB::getFPTOSINT(SrcVT, Promoted) in findFPToIntLibcall()
958 : RTLIB::getFPTOUINT(SrcVT, Promoted); in findFPToIntLibcall()
1671 EVT SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP() local
1684 if (SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1696 if (SrcVT.bitsLE(MVT::i64)) { in ExpandFloatRes_XINT_TO_FP()
1700 } else if (SrcVT.bitsLE(MVT::i128)) { in ExpandFloatRes_XINT_TO_FP()
1716 if (isSigned || SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1728 SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP()
1736 switch (SrcVT.getSimpleVT().SimpleTy) { in ExpandFloatRes_XINT_TO_FP()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td312 class isFloatType<ValueType SrcVT> {
313 bit ret = !or(!eq(SrcVT.Value, f16.Value),
314 !eq(SrcVT.Value, f32.Value),
315 !eq(SrcVT.Value, f64.Value),
316 !eq(SrcVT.Value, v2f16.Value),
317 !eq(SrcVT.Value, v4f16.Value),
318 !eq(SrcVT.Value, v8f16.Value),
319 !eq(SrcVT.Value, v16f16.Value),
320 !eq(SrcVT.Value, v2f32.Value),
321 !eq(SrcVT.Value, v4f32.Value),
[all …]
H A DAMDGPUISelLowering.cpp895 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable() argument
902 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; in isNarrowingProfitable()
1385 EVT SrcVT = Op.getOperand(0).getValueType(); in LowerEXTRACT_SUBVECTOR() local
1388 if (((SrcVT == MVT::v4f16 && VT == MVT::v2f16) || in LowerEXTRACT_SUBVECTOR()
1389 (SrcVT == MVT::v4i16 && VT == MVT::v2i16)) && in LowerEXTRACT_SUBVECTOR()
1393 if (((SrcVT == MVT::v8f16 && VT == MVT::v4f16) || in LowerEXTRACT_SUBVECTOR()
1394 (SrcVT == MVT::v8i16 && VT == MVT::v4i16)) && in LowerEXTRACT_SUBVECTOR()
1398 if (((SrcVT == MVT::v16f16 && VT == MVT::v8f16) || in LowerEXTRACT_SUBVECTOR()
1399 (SrcVT == MVT::v16i16 && VT == MVT::v8i16)) && in LowerEXTRACT_SUBVECTOR()
2565 EVT SrcVT = Src.getValueType(); in LowerUINT_TO_FP() local
[all …]
H A DSIISelLowering.h268 EVT SrcVT) const override;
327 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMFastISel.cpp200 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1342 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp() local
1358 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || in ARMEmitCmp()
1359 SrcVT == MVT::i1) { in ARMEmitCmp()
1373 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) in ARMEmitCmp()
1381 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1423 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp()
1426 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1537 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP() local
1538 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in SelectIToFP()
[all …]
H A DARMISelLowering.h455 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
612 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86FastISel.cpp86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
700 unsigned Src, EVT SrcVT, in X86FastEmitExtend() argument
702 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); in X86FastEmitExtend()
1237 EVT SrcVT = TLI.getValueType(DL, RV->getType()); in X86SelectRet() local
1240 if (SrcVT != DstVT) { in X86SelectRet()
1241 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) in X86SelectRet()
1249 if (SrcVT == MVT::i1) { in X86SelectRet()
1254 SrcVT = MVT::i8; in X86SelectRet()
1259 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); in X86SelectRet()
1545 MVT SrcVT = TLI.getSimpleValueType(DL, I->getOperand(0)->getType()); in X86SelectZExt() local
[all …]
H A DX86ISelLowering.cpp5900 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
5908 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) && in isExtractSubvectorCheap()
7527 EVT SrcVT = Op.getOperand(0).getValueType(); in getTargetConstantBitsFromNode() local
7528 unsigned NumSrcElts = SrcVT.getVectorNumElements(); in getTargetConstantBitsFromNode()
8506 EVT SrcVT = SrcVec.getValueType(); in getFauxShuffleMask() local
8507 if (!SrcVT.getScalarType().isByteSized()) in getFauxShuffleMask()
8510 unsigned SrcByte = SrcIdx * (SrcVT.getScalarSizeInBits() / 8); in getFauxShuffleMask()
8513 std::min<unsigned>(MinBitsPerElt, SrcVT.getScalarSizeInBits()); in getFauxShuffleMask()
8604 EVT SrcVT = Src.getValueType(); in getFauxShuffleMask() local
8606 if (!SrcVT.isSimple() || (SrcVT.getSizeInBits() % 128) != 0 || in getFauxShuffleMask()
[all …]
H A DX86SelectionDAGInfo.cpp249 EVT SrcVT = Src.getValueType(); in emitConstantSizeRepmov() local
253 DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)), in emitConstantSizeRepmov()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DTypePromotion.cpp931 EVT SrcVT = TLI->getValueType(DL, I->getType()); in run() local
932 if (SrcVT.isSimple() && TLI->isTypeLegal(SrcVT.getSimpleVT())) in run()
935 if (TLI->getTypeAction(*Ctx, SrcVT) != TargetLowering::TypePromoteInteger) in run()
938 EVT PromotedVT = TLI->getTypeToTransformTo(*Ctx, SrcVT); in run()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h360 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
362 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
385 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DRISCVISelLowering.cpp1170 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { in isTruncateFree() argument
1173 if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() || in isTruncateFree()
1176 unsigned SrcBits = SrcVT.getSizeInBits(); in isTruncateFree()
1196 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const { in isSExtCheaperThanZExt() argument
1197 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64; in isSExtCheaperThanZExt()
1463 bool RISCVTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
1469 if (ResVT.isScalableVector() || SrcVT.isScalableVector()) in isExtractSubvectorCheap()
1473 unsigned SrcElts = SrcVT.getVectorNumElements(); in isExtractSubvectorCheap()
1997 MVT SrcVT = Src.getSimpleValueType(); in lowerFP_TO_INT_SAT() local
1998 MVT SrcEltVT = SrcVT.getVectorElementType(); in lowerFP_TO_INT_SAT()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Transforms/Scalar/
H A DScalarizer.cpp748 auto *SrcVT = dyn_cast<FixedVectorType>(BCI.getSrcTy()); in visitBitCastInst() local
749 if (!DstVT || !SrcVT) in visitBitCastInst()
753 unsigned SrcNumElems = SrcVT->getNumElements(); in visitBitCastInst()
785 auto *MidTy = FixedVectorType::get(SrcVT->getElementType(), FanIn); in visitBitCastInst()
/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2738 static unsigned decideComp(EVT SrcVT, ISD::CondCode CC) { in decideComp() argument
2739 if (SrcVT.isFloatingPoint()) { in decideComp()
2740 if (SrcVT == MVT::f128) in decideComp()
2747 static EVT decideCompType(EVT SrcVT) { in decideCompType() argument
2748 if (SrcVT == MVT::f128) in decideCompType()
2750 return SrcVT; in decideCompType()
2753 static bool safeWithoutCompWithNull(EVT SrcVT, ISD::CondCode CC, in safeWithoutCompWithNull() argument
2755 if (SrcVT.isFloatingPoint()) { in safeWithoutCompWithNull()
2760 return SrcVT != MVT::f128; in safeWithoutCompWithNull()
2775 return isSignedIntSetCC(CC) && SrcVT == MVT::i64; in safeWithoutCompWithNull()
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2583 EVT SrcVT = In.getValueType(); in truncateVectorWithNARROW() local
2586 if (SrcVT == DstVT) in truncateVectorWithNARROW()
2589 unsigned SrcSizeInBits = SrcVT.getSizeInBits(); in truncateVectorWithNARROW()
2590 unsigned NumElems = SrcVT.getVectorNumElements(); in truncateVectorWithNARROW()
2597 EVT PackedSVT = EVT::getIntegerVT(Ctx, SrcVT.getScalarSizeInBits() / 2); in truncateVectorWithNARROW()
2602 if (SrcVT.getScalarSizeInBits() > 16) { in truncateVectorWithNARROW()
2615 if (SrcVT.is256BitVector() && DstVT.is128BitVector()) { in truncateVectorWithNARROW()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2929 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
2930 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && in isFPExtFree()
2947 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
2948 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFoldable()
2950 return isFPExtFree(DestVT, SrcVT); in isFPExtFoldable()
3071 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument

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