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Searched refs:ResVT (Results 1 – 25 of 34) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVECustomDAG.h164 SDValue getNode(unsigned OC, ArrayRef<EVT> ResVT, ArrayRef<SDValue> OpV,
166 auto N = DAG.getNode(OC, DL, ResVT, OpV);
172 SDValue getNode(unsigned OC, EVT ResVT, ArrayRef<SDValue> OpV,
174 auto N = DAG.getNode(OC, DL, ResVT, OpV);
184 SDValue getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, SDValue StartV,
H A DVVPInstrPatternsVec.td598 RegisterClass ResRC, ValueType ResVT,
601 def : Pat <(ResVT (!cast<SDPatternOperator>("vvp_reduce_"#VVPRedOp)
609 def : Pat <(ResVT (!cast<SDPatternOperator>("vvp_reduce_"#VVPRedOp)
618 RegisterClass ResRC, ValueType ResVT,
620 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "or", "VROR">;
621 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "and", "VRAND">;
622 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "xor", "VRXOR">;
623 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "add", "VSUM"#SumSuffix>;
624 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "smax", "VRMAX"#MinMaxSuffix>;
H A DVECustomDAG.cpp562 SDValue VECustomDAG::getLegalReductionOpVVP(unsigned VVPOpcode, EVT ResVT, in getLegalReductionOpVVP() argument
576 return getNode(ScalarOC, ResVT, {StartV, ReductionResV}); in getLegalReductionOpVVP()
583 getNode(VVPOpcode, ResVT, {StartV, VectorV, Mask, AVL}, Flags)); in getLegalReductionOpVVP()
586 getNode(VVPOpcode, ResVT, {VectorV, Mask, AVL}, Flags)); in getLegalReductionOpVVP()
H A DVVPISelLowering.cpp345 MVT ResVT = splitVectorType(Op.getValue(0).getSimpleValueType()); in splitVectorOp() local
388 CDAG.getNode(Op.getOpcode(), ResVT, OpVec, Op->getFlags()); in splitVectorOp()
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2370 EVT ResVT = N->getValueType(0); in performVectorExtendToFPCombine() local
2372 if (ResVT == MVT::v4f32 && (InVT == MVT::v4i16 || InVT == MVT::v4i8)) in performVectorExtendToFPCombine()
2374 else if (ResVT == MVT::v2f64 && (InVT == MVT::v2i16 || InVT == MVT::v2i8)) in performVectorExtendToFPCombine()
2382 return DAG.getNode(N->getOpcode(), SDLoc(N), ResVT, Conv); in performVectorExtendToFPCombine()
2404 EVT ResVT = N->getValueType(0); in performVectorExtendCombine() local
2405 if (ResVT == MVT::v8i16) { in performVectorExtendCombine()
2409 } else if (ResVT == MVT::v4i32) { in performVectorExtendCombine()
2413 } else if (ResVT == MVT::v2i64) { in performVectorExtendCombine()
2429 return DAG.getNode(Op, SDLoc(N), ResVT, Source); in performVectorExtendCombine()
2471 EVT ResVT; in performVectorTruncZeroCombine() local
[all …]
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp265 EVT ResVT = N->getValueType(0); in ScalarizeVecRes_OverflowOp() local
269 if (getTypeAction(ResVT) == TargetLowering::TypeScalarizeVector) { in ScalarizeVecRes_OverflowOp()
281 ResVT.getVectorElementType(), OvVT.getVectorElementType()); in ScalarizeVecRes_OverflowOp()
1667 EVT ResVT = N->getValueType(0); in SplitVecRes_OverflowOp() local
1670 std::tie(LoResVT, HiResVT) = DAG.GetSplitDestVTs(ResVT); in SplitVecRes_OverflowOp()
1674 if (getTypeAction(ResVT) == TargetLowering::TypeSplitVector) { in SplitVecRes_OverflowOp()
2964 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE() local
2979 return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags()); in SplitVecOp_VECREDUCE()
2983 EVT ResVT = N->getValueType(0); in SplitVecOp_VECREDUCE_SEQ() local
2998 SDValue Partial = DAG.getNode(N->getOpcode(), dl, ResVT, AccOp, Lo, Flags); in SplitVecOp_VECREDUCE_SEQ()
[all …]
H A DLegalizeIntegerTypes.cpp310 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0() local
312 N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
2280 EVT ResVT = N->getValueType(0); in PromoteIntOp_VECREDUCE() local
2304 if (ResVT.bitsGE(EltVT)) in PromoteIntOp_VECREDUCE()
2305 return DAG.getNode(Opcode, SDLoc(N), ResVT, Op); in PromoteIntOp_VECREDUCE()
2310 return DAG.getNode(ISD::TRUNCATE, dl, ResVT, Reduce); in PromoteIntOp_VECREDUCE()
5667 EVT ResVT = N->getValueType(0); in PromoteIntOp_CONCAT_VECTORS() local
5670 if (ResVT.isScalableVector()) { in PromoteIntOp_CONCAT_VECTORS()
5671 SDValue ResVec = DAG.getUNDEF(ResVT); in PromoteIntOp_CONCAT_VECTORS()
5676 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op, in PromoteIntOp_CONCAT_VECTORS()
H A DSelectionDAG.cpp1913 SDValue SelectionDAG::getStepVector(const SDLoc &DL, EVT ResVT) { in getStepVector() argument
1914 APInt One(ResVT.getScalarSizeInBits(), 1); in getStepVector()
1915 return getStepVector(DL, ResVT, One); in getStepVector()
1918 SDValue SelectionDAG::getStepVector(const SDLoc &DL, EVT ResVT, APInt StepVal) { in getStepVector() argument
1919 assert(ResVT.getScalarSizeInBits() == StepVal.getBitWidth()); in getStepVector()
1920 if (ResVT.isScalableVector()) in getStepVector()
1922 ISD::STEP_VECTOR, DL, ResVT, in getStepVector()
1923 getTargetConstant(StepVal, DL, ResVT.getVectorElementType())); in getStepVector()
1926 for (uint64_t i = 0; i < ResVT.getVectorNumElements(); i++) in getStepVector()
1928 getConstant(StepVal * i, DL, ResVT.getVectorElementType())); in getStepVector()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp5098 EVT ResVT = N->getValueType(0); in ReplaceLoadVector() local
5101 assert(ResVT.isVector() && "Vector load must have vector type"); in ReplaceLoadVector()
5106 assert(ResVT.isSimple() && "Can only handle simple types"); in ReplaceLoadVector()
5107 switch (ResVT.getSimpleVT().SimpleTy) { in ReplaceLoadVector()
5131 Align PrefAlign = TD.getPrefTypeAlign(ResVT.getTypeForEVT(*DAG.getContext())); in ReplaceLoadVector()
5141 EVT EltVT = ResVT.getVectorElementType(); in ReplaceLoadVector()
5142 unsigned NumElts = ResVT.getVectorNumElements(); in ReplaceLoadVector()
5213 Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res); in ReplaceLoadVector()
5220 SDValue BuildVec = DAG.getBuildVector(ResVT, DL, ScalarRes); in ReplaceLoadVector()
5243 EVT ResVT = N->getValueType(0); in ReplaceINTRINSIC_W_CHAIN() local
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1694 EVT ResVT = TLI->getValueType(DL, ResTy); in getExtendedReductionCost() local
1700 if (ST->hasMVEIntegerOps() && ValVT.isSimple() && ResVT.isSimple()) { in getExtendedReductionCost()
1709 unsigned RevVTSize = ResVT.getSizeInBits(); in getExtendedReductionCost()
1729 EVT ResVT = TLI->getValueType(DL, ResTy); in getMulAccReductionCost() local
1731 if (ST->hasMVEIntegerOps() && ValVT.isSimple() && ResVT.isSimple()) { in getMulAccReductionCost()
1740 unsigned RevVTSize = ResVT.getSizeInBits(); in getMulAccReductionCost()
H A DARMISelLowering.cpp16923 EVT ResVT = N->getValueType(0); in PerformVECREDUCE_ADDCombine() local
16928 if (ResVT == MVT::i32 && N0.getOpcode() == ISD::ADD && in PerformVECREDUCE_ADDCombine()
16931 SDValue Red0 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(0)); in PerformVECREDUCE_ADDCombine()
16932 SDValue Red1 = DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, N0.getOperand(1)); in PerformVECREDUCE_ADDCombine()
16933 return DAG.getNode(ISD::ADD, dl, ResVT, Red0, Red1); in PerformVECREDUCE_ADDCombine()
16967 if (ResVT != RetTy || N0->getOpcode() != ExtendCode) in PerformVECREDUCE_ADDCombine()
16976 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
16998 if (ResVT != RetTy) in PerformVECREDUCE_ADDCombine()
17003 ResVT.getScalarSizeInBits()) in PerformVECREDUCE_ADDCombine()
17028 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
[all …]
H A DARMISelLowering.h612 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1664 bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT, in shouldExpandGetActiveLaneMask() argument
1672 if (ResVT != MVT::nxv2i1 && ResVT != MVT::nxv4i1 && ResVT != MVT::nxv8i1 && in shouldExpandGetActiveLaneMask()
1673 ResVT != MVT::nxv16i1 && ResVT != MVT::v2i1 && ResVT != MVT::v4i1 && in shouldExpandGetActiveLaneMask()
1674 ResVT != MVT::v8i1 && ResVT != MVT::v16i1) in shouldExpandGetActiveLaneMask()
15029 bool AArch64TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
15031 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
15034 return (Index == 0 || Index == ResVT.getVectorMinNumElements()); in isExtractSubvectorCheap()
18876 EVT ResVT = N->getValueType(0); in performUzpCombine() local
18881 switch (ResVT.getSimpleVT().SimpleTy) { in performUzpCombine()
18900 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Trunc, in performUzpCombine()
[all …]
H A DAArch64ISelLowering.h690 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h385 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h327 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DSIISelLowering.cpp1641 bool SITargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
1643 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
4676 auto ResVT = DAG.GetSplitDestVTs(VT); in splitTernaryVectorOp() local
4678 SDValue OpLo = DAG.getNode(Opc, SL, ResVT.first, Lo0, Lo1, Lo2, in splitTernaryVectorOp()
4680 SDValue OpHi = DAG.getNode(Opc, SL, ResVT.second, Hi0, Hi1, Hi2, in splitTernaryVectorOp()
10795 EVT ResVT = N->getValueType(0); in performExtractVectorEltCombine() local
10805 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, ResVT, Vec.getOperand(0), Idx); in performExtractVectorEltCombine()
10806 return DAG.getNode(Vec.getOpcode(), SL, ResVT, Elt); in performExtractVectorEltCombine()
10814 if (Vec.hasOneUse() && DCI.isBeforeLegalize() && VecEltVT == ResVT) { in performExtractVectorEltCombine()
10835 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, ResVT, in performExtractVectorEltCombine()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3511 EVT ResVT = Op.getValueType(); in lowerBITCAST() local
3518 SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(), in lowerBITCAST()
3525 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
3541 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
6051 SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT, in combineExtract() argument
6079 return DAG.getUNDEF(ResVT); in combineExtract()
6109 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits()); in combineExtract()
6111 if (VT != ResVT) { in combineExtract()
6113 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op); in combineExtract()
6149 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h169 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
H A DHexagonISelLowering.cpp2154 bool HexagonTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
2156 assert(ResVT.getVectorElementType() == SrcVT.getVectorElementType()); in isExtractSubvectorCheap()
2157 if (!ResVT.isSimple() || !SrcVT.isSimple()) in isExtractSubvectorCheap()
2160 MVT ResTy = ResVT.getSimpleVT(), SrcTy = SrcVT.getSimpleVT(); in isExtractSubvectorCheap()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp5900 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
5902 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
5907 if (ResVT.getVectorElementType() == MVT::i1) in isExtractSubvectorCheap()
5908 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) && in isExtractSubvectorCheap()
5909 (Index == ResVT.getVectorNumElements())); in isExtractSubvectorCheap()
5911 return (Index % ResVT.getVectorNumElements()) == 0; in isExtractSubvectorCheap()
11597 MVT ResVT = Op.getSimpleValueType(); in LowerAVXCONCAT_VECTORS() local
11599 assert((ResVT.is256BitVector() || in LowerAVXCONCAT_VECTORS()
11600 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide"); in LowerAVXCONCAT_VECTORS()
11624 MVT HalfVT = ResVT.getHalfNumVectorElementsVT(); in LowerAVXCONCAT_VECTORS()
[all …]
H A DX86FastISel.cpp3563 EVT ResVT = VA.getValVT(); in fastLowerCall() local
3564 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3565 unsigned MemSize = ResVT.getSizeInBits()/8; in fastLowerCall()
3570 Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt; in fastLowerCall()
H A DX86ISelLowering.h1415 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp7903 EVT ResVT = Op.getValueType(); in LowerSELECT_CC() local
7962 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
7965 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7975 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
7984 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7998 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
8001 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
8008 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
8014 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
8020 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
[all …]
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h1652 EVT ResVT = getTLI()->getValueType(DL, RetTy, true); in getIntrinsicInstrCost() local
1657 if (!getTLI()->shouldExpandGetActiveLaneMask(ResVT, ArgType)) { in getIntrinsicInstrCost()

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