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Searched refs:REG (Results 1 – 25 of 605) sorted by relevance

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/openbsd-src/gnu/usr.bin/binutils-2.17/opcodes/
H A Dm88k-dis.c40 …{0xf400c800,"jsr ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JSR , 0,0…
41 …{0xf400cc00,"jsr.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JSR , 0,0…
42 …{0xf400c000,"jmp ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JMP , 0,0…
43 …{0xf400c400,"jmp.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JMP , 0,0…
48 …{0xd0000000,"bb0 ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB0, i16bit,0,1,0,0…
49 …{0xd4000000,"bb0.n ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB0, i16bit,0,1,0,0…
50 …{0xd8000000,"bb1 ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB1, i16bit,0,1,0,0…
51 …{0xdc000000,"bb1.n ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB1, i16bit,0,1,0,0…
52 …{0xf000d000,"tb0 ",{21,5,HEX} ,{16,5,REG} ,{0,10,HEX}, {2,2,NA,TB0 , i10bit,0,1,0,0…
53 …{0xf000d800,"tb1 ",{21,5,HEX} ,{16,5,REG} ,{0,10,HEX}, {2,2,NA,TB1 , i10bit,0,1,0,0…
[all …]
H A Darc-opc.c313 #define REG (MODDOT + 1) macro
317 #define AUXREG (REG + 1)
1056 if (type == REG) in lookup_register()
1139 const struct arc_operand_value *reg = lookup_register (REG, regno); in extract_reg()
1421 { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 },
1422 { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 },
1423 { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 },
1424 { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 },
1425 { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 },
1426 { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 },
[all …]
/openbsd-src/gnu/usr.bin/binutils/opcodes/
H A Dm88k-dis.c37 …{0xf400c800,"jsr ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JSR , 0,0…
38 …{0xf400cc00,"jsr.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JSR , 0,0…
39 …{0xf400c000,"jmp ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JMP , 0,0…
40 …{0xf400c400,"jmp.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JMP , 0,0…
45 …{0xd0000000,"bb0 ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB0, i16bit,0,1,0,0…
46 …{0xd4000000,"bb0.n ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB0, i16bit,0,1,0,0…
47 …{0xd8000000,"bb1 ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB1, i16bit,0,1,0,0…
48 …{0xdc000000,"bb1.n ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB1, i16bit,0,1,0,0…
49 …{0xf000d000,"tb0 ",{21,5,HEX} ,{16,5,REG} ,{0,10,HEX}, {2,2,NA,TB0 , i10bit,0,1,0,0…
50 …{0xf000d800,"tb1 ",{21,5,HEX} ,{16,5,REG} ,{0,10,HEX}, {2,2,NA,TB1 , i10bit,0,1,0,0…
[all …]
H A Darc-opc.c271 #define REG (MODDOT + 1) macro
275 #define AUXREG (REG + 1)
360 { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 },
361 { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 },
362 { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 },
363 { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 },
364 { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 },
365 { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 },
366 { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 },
367 { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 },
[all …]
/openbsd-src/gnu/usr.bin/binutils/include/opcode/
H A Di960.h40 #define REG 3 macro
284 { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } },
285 { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } },
286 { R_3(0x582), "andnot", I_BASE, REG, 3, { RSL,RSL,RS } },
287 { R_3(0x583), "setbit", I_BASE, REG, 3, { RSL,RSL,RS } },
288 { R_3(0x584), "notand", I_BASE, REG, 3, { RSL,RSL,RS } },
289 { R_3(0x586), "xor", I_BASE, REG, 3, { RSL,RSL,RS } },
290 { R_3(0x587), "or", I_BASE, REG, 3, { RSL,RSL,RS } },
291 { R_3(0x588), "nor", I_BASE, REG, 3, { RSL,RSL,RS } },
292 { R_3(0x589), "xnor", I_BASE, REG, 3, { RSL,RSL,RS } },
[all …]
/openbsd-src/gnu/usr.bin/binutils-2.17/include/opcode/
H A Di960.h40 #define REG 3 macro
284 { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } },
285 { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } },
286 { R_3(0x582), "andnot", I_BASE, REG, 3, { RSL,RSL,RS } },
287 { R_3(0x583), "setbit", I_BASE, REG, 3, { RSL,RSL,RS } },
288 { R_3(0x584), "notand", I_BASE, REG, 3, { RSL,RSL,RS } },
289 { R_3(0x586), "xor", I_BASE, REG, 3, { RSL,RSL,RS } },
290 { R_3(0x587), "or", I_BASE, REG, 3, { RSL,RSL,RS } },
291 { R_3(0x588), "nor", I_BASE, REG, 3, { RSL,RSL,RS } },
292 { R_3(0x589), "xnor", I_BASE, REG, 3, { RSL,RSL,RS } },
[all …]
/openbsd-src/sys/arch/sh/sh/
H A Ddevreg.c101 SH ## x ## REG(TRA); \
102 SH ## x ## REG(EXPEVT); \
103 SH ## x ## REG(INTEVT); \
105 SH ## x ## REG(BARA); \
106 SH ## x ## REG(BAMRA); \
107 SH ## x ## REG(BASRA); \
108 SH ## x ## REG(BBRA); \
109 SH ## x ## REG(BARB); \
110 SH ## x ## REG(BAMRB); \
111 SH ## x ## REG(BASRB); \
[all …]
/openbsd-src/sys/dev/pci/drm/i915/gt/
H A Dintel_lrc.c54 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets() macro
110 REG(0x034),
111 REG(0x030),
112 REG(0x038),
113 REG(0x03c),
114 REG(0x168),
115 REG(0x140),
116 REG(0x110),
117 REG(0x11c),
118 REG(0x114),
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/gpio/dcn10/
H A Dhw_translate_dcn10.c51 #define REG(reg_name)\ macro
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/gpio/dce120/
H A Dhw_translate_dce120.c51 #define REG(reg_name)\ macro
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/gpio/dcn20/
H A Dhw_translate_dcn20.c54 #undef REG
55 #define REG(reg_name)\ macro
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
155 case REG(DC_GPIO_DDC1_A): in offset_to_id()
158 case REG(DC_GPIO_DDC2_A): in offset_to_id()
161 case REG(DC_GPIO_DDC3_A): in offset_to_id()
164 case REG(DC_GPIO_DDC4_A): in offset_to_id()
167 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/gpio/dcn30/
H A Dhw_translate_dcn30.c61 #undef REG
62 #define REG(reg_name)\ macro
80 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
110 case REG(DC_GPIO_HPD_A): in offset_to_id()
137 case REG(DC_GPIO_GENLK_A): in offset_to_id()
162 case REG(DC_GPIO_DDC1_A): in offset_to_id()
165 case REG(DC_GPIO_DDC2_A): in offset_to_id()
168 case REG(DC_GPIO_DDC3_A): in offset_to_id()
171 case REG(DC_GPIO_DDC4_A): in offset_to_id()
174 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/openbsd-src/gnu/usr.bin/binutils-2.17/gas/config/
H A Dbfin-parse.y396 %token REG
523 %type <reg> REG
717 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
747 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
748 COLON expr COMMA REG COLON expr RPAREN aligndir
763 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
764 REG COLON expr RPAREN aligndir
779 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
791 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
801 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_dwb_cm.c36 #define REG(reg)\ macro
89 gam_regs.start_cntl_b = REG(DWB_OGAM_RAMA_START_CNTL_B); in dwb3_program_ogam_luta_settings()
90 gam_regs.start_cntl_g = REG(DWB_OGAM_RAMA_START_CNTL_G); in dwb3_program_ogam_luta_settings()
91 gam_regs.start_cntl_r = REG(DWB_OGAM_RAMA_START_CNTL_R); in dwb3_program_ogam_luta_settings()
92 gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMA_START_BASE_CNTL_B); in dwb3_program_ogam_luta_settings()
93 gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMA_START_BASE_CNTL_G); in dwb3_program_ogam_luta_settings()
94 gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMA_START_BASE_CNTL_R); in dwb3_program_ogam_luta_settings()
95 gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_B); in dwb3_program_ogam_luta_settings()
96 gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_G); in dwb3_program_ogam_luta_settings()
97 gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_R); in dwb3_program_ogam_luta_settings()
[all …]
H A Ddcn30_dpp_cm.c33 #define REG(reg)\ macro
247 gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMB_START_CNTL_B); in dpp3_program_gamcor_lut()
248 gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMB_START_CNTL_G); in dpp3_program_gamcor_lut()
249 gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMB_START_CNTL_R); in dpp3_program_gamcor_lut()
250 gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B); in dpp3_program_gamcor_lut()
251 gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G); in dpp3_program_gamcor_lut()
252 gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R); in dpp3_program_gamcor_lut()
253 gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMB_END_CNTL1_B); in dpp3_program_gamcor_lut()
254 gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMB_END_CNTL2_B); in dpp3_program_gamcor_lut()
255 gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMB_END_CNTL1_G); in dpp3_program_gamcor_lut()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_cm.c42 #define REG(reg)\ macro
125 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); in program_gamut_remap()
126 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); in program_gamut_remap()
135 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); in program_gamut_remap()
136 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); in program_gamut_remap()
145 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); in program_gamut_remap()
146 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); in program_gamut_remap()
220 gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12); in dpp1_cm_program_color_matrix()
221 gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34); in dpp1_cm_program_color_matrix()
225 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); in dpp1_cm_program_color_matrix()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/gpio/dcn32/
H A Dhw_translate_dcn32.c52 #undef REG
53 #define REG(reg_name)\ macro
71 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
98 case REG(DC_GPIO_HPD_A): in offset_to_id()
122 case REG(DC_GPIO_GENLK_A): in offset_to_id()
146 case REG(DC_GPIO_DDC1_A): in offset_to_id()
149 case REG(DC_GPIO_DDC2_A): in offset_to_id()
152 case REG(DC_GPIO_DDC3_A): in offset_to_id()
155 case REG(DC_GPIO_DDC4_A): in offset_to_id()
158 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/gpio/dcn21/
H A Dhw_translate_dcn21.c54 #undef REG
55 #define REG(reg_name)\ macro
72 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
106 case REG(DC_GPIO_HPD_A): in offset_to_id()
133 case REG(DC_GPIO_GENLK_A): in offset_to_id()
158 case REG(DC_GPIO_DDC1_A): in offset_to_id()
161 case REG(DC_GPIO_DDC2_A): in offset_to_id()
164 case REG(DC_GPIO_DDC3_A): in offset_to_id()
167 case REG(DC_GPIO_DDC4_A): in offset_to_id()
170 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/gpio/dcn315/
H A Dhw_translate_dcn315.c54 #undef REG
55 #define REG(reg_name)\ macro
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
155 case REG(DC_GPIO_DDC1_A): in offset_to_id()
158 case REG(DC_GPIO_DDC2_A): in offset_to_id()
161 case REG(DC_GPIO_DDC3_A): in offset_to_id()
164 case REG(DC_GPIO_DDC4_A): in offset_to_id()
167 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/openbsd-src/sys/arch/luna88k/stand/boot/
H A Dsio.c96 int rr0 = sioreg(REG(unit, RR0), 0); in siointr()
97 int rr1 = sioreg(REG(unit, RR1), 0); in siointr()
104 sioreg(REG(unit, WR0), WR0_ERRRST); /* Channel-A Error Reset */ in siointr()
188 while ((sioreg(REG(unit, RR0), 0) & RR0_TXEMPTY) == 0); in siocnputc()
193 while ((sioreg(REG(unit, RR0), 0) & RR0_TXEMPTY) == 0); in siocnputc()
204 sioreg(REG(0, WR0), WR0_CHANRST); /* Channel-A Reset */ in sioinit()
209 sioreg(REG(0, WR0), WR0_RSTINT); /* Reset E/S Interrupt */ in sioinit()
210 sioreg(REG(0, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY); /* Tx/Rx */ in sioinit()
211 sioreg(REG(0, WR3), WR3_RX8BIT | WR3_RXENBL); /* Rx */ in sioinit()
212 sioreg(REG(0, WR5), WR5_TX8BIT | WR5_TXENBL | WR5_DTR | WR5_RTS); /* Tx */ in sioinit()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCReturnProtectorLowering.cpp40 unsigned REG = MF.getFrameInfo().getReturnProtectorRegister(); in insertReturnProtectorPrologue() local
67 BuildMI(MBB, MI, MBBDL, TII->get(PPC::ADDIStocHA8), REG) in insertReturnProtectorPrologue()
70 BuildMI(MBB, MI, MBBDL, TII->get(PPC::LD), REG) in insertReturnProtectorPrologue()
72 .addReg(REG); in insertReturnProtectorPrologue()
74 BuildMI(MBB, MI, MBBDL, TII->get(XOR), REG) in insertReturnProtectorPrologue()
75 .addReg(REG) in insertReturnProtectorPrologue()
82 BuildMI(MBB, MI, MBBDL, TII->get(PPC::RETGUARD_LOAD_PC), REG) in insertReturnProtectorPrologue()
86 BuildMI(MBB, MI, MBBDL, TII->get(PPC::RETGUARD_LOAD_GOT), REG) in insertReturnProtectorPrologue()
87 .addReg(REG) in insertReturnProtectorPrologue()
89 BuildMI(MBB, MI, MBBDL, TII->get(PPC::LWZtoc), REG) in insertReturnProtectorPrologue()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c33 #define REG(reg)\ macro
170 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); in mpc2_set_output_csc()
171 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); in mpc2_set_output_csc()
173 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); in mpc2_set_output_csc()
174 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); in mpc2_set_output_csc()
229 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); in mpc2_set_ocsc_default()
230 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); in mpc2_set_ocsc_default()
232 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); in mpc2_set_ocsc_default()
233 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); in mpc2_set_ocsc_default()
330 gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]); in mpc2_program_lutb()
[all …]
/openbsd-src/gnu/llvm/lldb/source/Plugins/Process/FreeBSDKernel/
H A DRegisterContextFreeBSDKernel_x86_64.cpp62 #define REG(x) \ in ReadRegister() macro
67 REG(r15); in ReadRegister()
68 REG(r14); in ReadRegister()
69 REG(r13); in ReadRegister()
70 REG(r12); in ReadRegister()
71 REG(rbp); in ReadRegister()
72 REG(rsp); in ReadRegister()
73 REG(rbx); in ReadRegister()
74 REG(rip); in ReadRegister()
76 #undef REG in ReadRegister()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ReturnProtectorLowering.cpp40 unsigned REG = MF.getFrameInfo().getReturnProtectorRegister(); in insertReturnProtectorPrologue() local
42 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::ADRP), REG) in insertReturnProtectorPrologue()
44 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::LDRXui), REG) in insertReturnProtectorPrologue()
45 .addReg(REG) in insertReturnProtectorPrologue()
47 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::EORXrr), REG) in insertReturnProtectorPrologue()
48 .addReg(REG) in insertReturnProtectorPrologue()
58 unsigned REG = MF.getFrameInfo().getReturnProtectorRegister(); in insertReturnProtectorEpilogue() local
64 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::EORXrr), REG) in insertReturnProtectorEpilogue()
65 .addReg(REG) in insertReturnProtectorEpilogue()
72 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::SUBSXrr), REG) in insertReturnProtectorEpilogue()
[all …]
/openbsd-src/gnu/usr.bin/gcc/gcc/config/d30v/
H A Dd30v.c375 return (GET_CODE (addr) == REG);
432 if (GET_CODE (op) != REG)
437 case REG:
462 if (GET_CODE (SUBREG_REG (op)) != REG)
468 if (GET_CODE (op) != REG)
486 if (GET_CODE (SUBREG_REG (op)) != REG)
492 if (GET_CODE (op) != REG)
510 if (GET_CODE (SUBREG_REG (op)) != REG)
516 if (GET_CODE (op) != REG)
537 if (GET_CODE (SUBREG_REG (op)) != REG)
[all …]

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