Searched refs:OpEntry (Results 1 – 2 of 2) sorted by relevance
1625 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in selectDivRem() local1637 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy), in selectDivRem()1641 if (OpEntry.OpSignExtend) { in selectDivRem()1642 if (OpEntry.IsOpSigned) in selectDivRem()1644 TII.get(OpEntry.OpSignExtend)); in selectDivRem()1671 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem)) in selectDivRem()1683 OpEntry.DivRemResultReg == X86::AH && STI.is64Bit()) { in selectDivRem()1705 .addReg(OpEntry.DivRemResultReg); in selectDivRem()
1946 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in X86SelectDivRem() local1956 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg); in X86SelectDivRem()1958 if (OpEntry.OpSignExtend) { in X86SelectDivRem()1959 if (OpEntry.IsOpSigned) in X86SelectDivRem()1961 TII.get(OpEntry.OpSignExtend)); in X86SelectDivRem()1987 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()1999 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { in X86SelectDivRem()2017 .addReg(OpEntry.DivRemResultReg); in X86SelectDivRem()