| /openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFrameLowering.cpp | 295 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
296 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg) in emitPrologue()
300 .addReg(OffsetReg); in emitPrologue()
347 Register OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
348 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg) in emitEpilogue()
356 .addReg(OffsetReg); in emitEpilogue()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 50 unsigned OffsetReg,
56 unsigned OffsetReg,
246 unsigned OffsetReg) const;
254 unsigned OffsetReg) const;
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| H A D | R600InstrInfo.cpp | 1014 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1015 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1020 OffsetReg); in expandPostRAPseudo()
1028 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1029 if (OffsetReg == R600::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1035 OffsetReg); in expandPostRAPseudo()
1090 unsigned OffsetReg) const { in buildIndirectWrite()
1091 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1097 unsigned OffsetReg, in buildIndirectWrite() argument
1108 R600::AR_X, OffsetReg); in buildIndirectWrite()
[all …]
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| H A D | AMDGPUCallLowering.cpp | 223 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress() local
225 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); in getStackAddress()
404 auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset); in lowerParameterPtr() local
406 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg); in lowerParameterPtr()
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| H A D | SIRegisterInfo.cpp | 831 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in materializeFrameBaseRegister() local
837 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in materializeFrameBaseRegister()
844 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
850 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
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| H A D | AMDGPUInstructionSelector.cpp | 893 Register OffsetReg = MI.getOperand(2).getReg(); in selectG_SBFX_UBFX() local
908 .addReg(OffsetReg) in selectG_SBFX_UBFX()
3795 if (Register OffsetReg = in selectSmrdOffset() local
3798 *SOffset = OffsetReg; in selectSmrdOffset()
3828 if (Register OffsetReg = matchZeroExtendFromS32(*MRI, GEPI.SgprParts[1])) { in selectSmrdOffset() local
3830 *SOffset = OffsetReg; in selectSmrdOffset()
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| H A D | AMDGPURegisterBankInfo.cpp | 1468 Register OffsetReg = MI.getOperand(FirstOpnd + 1).getReg(); in applyMappingBFE() local
1484 auto ShiftOffset = Signed ? B.buildAShr(S64, SrcReg, OffsetReg) in applyMappingBFE()
1485 : B.buildLShr(S64, SrcReg, OffsetReg); in applyMappingBFE()
1537 auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask); in applyMappingBFE()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 134 unsigned OffsetReg; member
180 return Mem.OffsetReg; in getMemOffsetReg()
620 Op->Mem.OffsetReg = 0; in MorphToMemImm()
628 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
632 Op->Mem.OffsetReg = OffsetReg; in MorphToMemRegReg()
644 Op->Mem.OffsetReg = 0; in MorphToMemRegImm()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 62 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
63 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 565 unsigned OffsetReg = 0; in ReduceLoadStore() local
569 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
604 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
607 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
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| H A D | ARMCallLowering.cpp | 104 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress() local
106 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| H A D | Thumb2InstrInfo.cpp | 627 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg(); in rewriteT2FrameIndex() local
628 if (OffsetReg != 0) { in rewriteT2FrameIndex()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 100 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
102 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| H A D | X86ISelLowering.cpp | 35368 unsigned OffsetReg = 0; in EmitVAARGWithCustomInserter() local
35422 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); in EmitVAARGWithCustomInserter()
35423 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) in EmitVAARGWithCustomInserter()
35433 .addReg(OffsetReg) in EmitVAARGWithCustomInserter()
35444 assert(OffsetReg != 0); in EmitVAARGWithCustomInserter()
35464 .addReg(OffsetReg) in EmitVAARGWithCustomInserter()
35474 .addReg(OffsetReg) in EmitVAARGWithCustomInserter()
35481 .addReg(OffsetReg) in EmitVAARGWithCustomInserter()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 257 unsigned OffsetReg; member
349 return Mem.OffsetReg; in getMemOffsetReg()
543 Op->Mem.OffsetReg = offsetReg; in MorphToMEMrr()
552 Op->Mem.OffsetReg = Sparc::G0; // always 0 in CreateMEMr()
564 Op->Mem.OffsetReg = 0; in MorphToMEMri()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 238 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); in getStackAddress() local
239 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| H A D | MipsSEInstrInfo.cpp | 895 Register OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
909 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); in expandEhReturn()
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| H A D | MipsISelLowering.cpp | 2559 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; in lowerEH_RETURN() local
2561 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); in lowerEH_RETURN()
2564 DAG.getRegister(OffsetReg, Ty), in lowerEH_RETURN()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 168 Register OffsetReg = MI.getOperand(2).getReg(); in canRemoveAddasl() local
173 if (OffsetReg == RR.Reg) { in canRemoveAddasl()
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| H A D | HexagonISelLowering.cpp | 3300 unsigned OffsetReg = Hexagon::R28; in LowerEH_RETURN() local
3306 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset); in LowerEH_RETURN()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 265 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset); in getStackAddress() local
267 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| H A D | AArch64InstructionSelector.cpp | 6133 Register OffsetReg = OffsetInst->getOperand(1).getReg(); in selectExtendedSHL() local
6143 std::swap(OffsetReg, ConstantReg); in selectExtendedSHL()
6176 MachineInstr *ExtInst = getDefIgnoringCopies(OffsetReg, MRI); in selectExtendedSHL()
6185 OffsetReg = ExtInst->getOperand(1).getReg(); in selectExtendedSHL()
6190 OffsetReg = moveScalarRegClass(OffsetReg, AArch64::GPR32RegClass, MIB); in selectExtendedSHL()
6196 [=](MachineInstrBuilder &MIB) { MIB.addUse(OffsetReg); }, in selectExtendedSHL()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 95 unsigned OffsetReg = 0; member in __anond3c64d190111::AArch64FastISel::Address
121 OffsetReg = Reg; in setOffsetReg()
125 return OffsetReg; in getOffsetReg()
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