| /openbsd-src/gnu/llvm/llvm/lib/Target/Xtensa/ |
| H A D | XtensaTargetMachine.cpp | 35 bool IsLittle) { in computeDataLayout() argument
53 bool IsLittle) in XtensaTargetMachine() argument
54 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, IsLittle), TT, in XtensaTargetMachine()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/ObjCopy/ |
| H A D | CommonConfig.h | 41 MachineInfo(uint16_t EM, uint8_t ABI, bool Is64, bool IsLittle) in MachineInfo()
42 : EMachine(EM), OSABI(ABI), Is64Bit(Is64), IsLittleEndian(IsLittle) {} in MachineInfo()
44 MachineInfo(uint16_t EM, bool Is64, bool IsLittle) in MachineInfo()
45 : MachineInfo(EM, ELF::ELFOSABI_NONE, Is64, IsLittle) {} in MachineInfo()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMSubtarget.h | 214 bool IsLittle; variable
235 const ARMBaseTargetMachine &TM, bool IsLittle,
463 bool isLittle() const { return IsLittle; } in isLittle()
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| H A D | ARMSubtarget.cpp | 95 const ARMBaseTargetMachine &TM, bool IsLittle, in ARMSubtarget() argument
99 IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM), in ARMSubtarget()
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| H A D | ARMCallLowering.cpp | 159 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle(); in assignCustomValue() local
160 if (!IsLittle) in assignCustomValue()
336 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle(); in assignCustomValue() local
337 if (!IsLittle) in assignCustomValue()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsSubtarget.h | 76 bool IsLittle; variable
284 bool isLittle() const { return IsLittle; } in isLittle()
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| H A D | MipsISelLowering.cpp | 2691 bool IsLittle = Subtarget.isLittle(); in lowerLOAD() local
2705 IsLittle ? 7 : 0); in lowerLOAD()
2707 IsLittle ? 0 : 7); in lowerLOAD()
2711 IsLittle ? 3 : 0); in lowerLOAD()
2713 IsLittle ? 0 : 3); in lowerLOAD()
2761 bool IsLittle) { in lowerUnalignedIntStore() argument
2773 IsLittle ? 3 : 0); in lowerUnalignedIntStore()
2774 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); in lowerUnalignedIntStore()
2784 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); in lowerUnalignedIntStore()
2785 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); in lowerUnalignedIntStore()
[all …]
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| H A D | MipsSubtarget.cpp | 75 MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false), in MipsSubtarget()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64Subtarget.h | 125 bool IsLittle; variable
259 bool isLittleEndian() const { return IsLittle; } in isLittleEndian()
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| H A D | AArch64Subtarget.cpp | 298 IsLittle(LittleEndian), in AArch64Subtarget()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCCodeEmitter.h | 39 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) in MipsMCCodeEmitter() argument
40 : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {} in MipsMCCodeEmitter()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 56 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle) in ARMMCCodeEmitter() argument
57 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) { in ARMMCCodeEmitter()
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