| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 180 .addReg(TargetReg, RegState::ImplicitDefine); in buildGitPtr()
746 .addReg(ScratchRsrcReg, RegState::ImplicitDefine) in emitEntryFunctionScratchRsrcRegSetup()
780 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
795 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
806 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
810 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
816 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
820 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
847 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
851 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchRsrcRegSetup()
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| H A D | SIRegisterInfo.cpp | 213 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
230 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
1560 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1603 AccRead.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1652 MIB.addReg(ValueReg, RegState::ImplicitDefine); in buildSpillLoadStore()
1753 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillSGPR()
1849 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
1882 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in restoreSGPR()
1963 MIB.addReg(SB.SuperReg, RegState::ImplicitDefine); in spillEmergencySGPR()
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| H A D | SILowerControlFlow.cpp | 238 .addReg(Exec, RegState::ImplicitDefine); in emitIf()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 235 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in convertToBRCT()
680 RegState::ImplicitDefine | RegState::Dead); in fuseCompareOperations()
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| H A D | SystemZShortenInst.cpp | 148 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in shortenOn001AddCC()
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| H A D | SystemZFrameLowering.cpp | 434 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
1181 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
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| H A D | SystemZInstrInfo.cpp | 228 .addReg(Reg64, RegState::ImplicitDefine); in expandLoadStackGuard()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 63 ImplicitDefine = Implicit | Define, enumerator
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| /openbsd-src/gnu/llvm/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.cpp | 537 .addReg(Reg, RegState::ImplicitDefine) in ExpandMOVEM()
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| H A D | M68kFrameLowering.cpp | 889 I.addReg(Info.getReg(), RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1109 .addDef(Hexagon::R29, RegState::ImplicitDefine) in expandPostRAPseudo()
1110 .addDef(Hexagon::R30, RegState::ImplicitDefine) in expandPostRAPseudo()
1111 .addDef(Hexagon::R14, RegState::ImplicitDefine) in expandPostRAPseudo()
1112 .addDef(Hexagon::R15, RegState::ImplicitDefine) in expandPostRAPseudo()
1113 .addDef(Hexagon::R28, RegState::ImplicitDefine); in expandPostRAPseudo()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2197 .addReg(Pred[1].getReg(), RegState::ImplicitDefine); in PredicateInstruction()
2220 .addReg(Pred[1].getReg(), RegState::ImplicitDefine); in PredicateInstruction()
2279 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine); in PredicateInstruction()
2282 .addReg(PPC::RM, RegState::ImplicitDefine); in PredicateInstruction()
2833 .addReg(CRReg, RegState::ImplicitDefine); in optimizeCmpPostRA()
3295 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine); in replaceInstrWithLI()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 246 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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| H A D | ARMExpandPseudoInsts.cpp | 677 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
845 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
2694 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
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| H A D | ARMFrameLowering.cpp | 1933 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
1950 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
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| H A D | ARMBaseInstrInfo.cpp | 1448 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1494 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1524 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1549 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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| H A D | ARMLoadStoreOptimizer.cpp | 960 MIB.addReg(ImpDef, RegState::ImplicitDefine); in MergeOpsUpdate()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 2133 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
2134 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()
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| H A D | MipsSEInstrInfo.cpp | 134 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
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| H A D | MipsSEISelDAGToDAG.cpp | 57 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef; in addDSPCtrlRegOperands()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 1096 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | in EmitMachineNode()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 4954 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
4984 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
5059 MIB.addReg(Reg, RegState::ImplicitDefine); in expandPostRAPseudo()
5833 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
5855 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
5864 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
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| /openbsd-src/gnu/llvm/llvm/docs/ |
| H A D | MIRLangRef.rst | 553 - ``RegState::ImplicitDefine``
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 1606 Flags |= RegState::ImplicitDefine; in parseRegisterFlag()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2663 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); in emitSjLjDispatchBlock()
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