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Searched refs:FalseReg (Results 1 – 20 of 20) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86CmovConversion.cpp728 Register FalseReg = in convertCmovInstsToBranches() local
732 auto FRIt = FalseBBRegRewriteTable.find(FalseReg); in convertCmovInstsToBranches()
735 FalseReg = FRIt->second; in convertCmovInstsToBranches()
737 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg; in convertCmovInstsToBranches()
H A DX86InstrInfo.h362 Register FalseReg) const override;
H A DX86InstrInfo.cpp3358 Register FalseReg, int &CondCycles, in canInsertSelect() argument
3372 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
3396 Register FalseReg) const { in insertSelect()
3404 .addReg(FalseReg) in insertSelect()
/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp504 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
506 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
530 FalseReg.setImplicit(); in optimizeSelect()
531 NewMI.add(FalseReg); in optimizeSelect()
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp922 Register FalseReg = getRegForValue(Select->getFalseValue()); in selectSelect() local
923 if (FalseReg == 0) in selectSelect()
927 std::swap(TrueReg, FalseReg); in selectSelect()
966 .addReg(FalseReg) in selectSelect()
H A DWebAssemblyISelLowering.cpp478 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
483 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
516 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg); in LowerFPToInt()
520 .addReg(FalseReg) in LowerFPToInt()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp540 Register FalseReg, int &CondCycles, in canInsertSelect() argument
552 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
576 Register FalseReg) const { in insertSelect()
596 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); in insertSelect()
598 FalseReg = FReg; in insertSelect()
609 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
H A DSystemZInstrInfo.h245 Register FalseReg) const override;
H A DSystemZISelLowering.cpp7562 Register FalseReg = MI->getOperand(2).getReg(); in createPHIsForSelects() local
7568 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
7573 if (RegRewriteTable.find(FalseReg) != RegRewriteTable.end()) in createPHIsForSelects()
7574 FalseReg = RegRewriteTable[FalseReg].second; in createPHIsForSelects()
7579 .addReg(FalseReg).addMBB(FalseMBB); in createPHIsForSelects()
7582 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1531 Register FalseReg, int &CondCycles, in canInsertSelect() argument
1549 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
1575 Register FalseReg) const { in insertSelect()
1582 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
1634 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1635 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
3223 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
3230 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3232 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3234 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
H A DPPCInstrInfo.h557 Register FalseReg) const override;
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp788 auto FalseReg = MIB.getReg(3); in selectSelect() local
790 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
795 .addUse(FalseReg) in selectSelect()
H A DARMBaseInstrInfo.cpp2368 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1); in optimizeSelect() local
2371 const TargetRegisterClass *FalseClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
2404 FalseReg.setImplicit(); in optimizeSelect()
2405 NewMI.add(FalseReg); in optimizeSelect()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h313 Register TrueReg, Register FalseReg, int &CondCycles,
319 Register TrueReg, Register FalseReg) const override;
324 Register TrueReg, Register FalseReg) const;
H A DSIInstrInfo.cpp1134 Register FalseReg) const { in insertVectorSelect()
1147 .addReg(FalseReg) in insertVectorSelect()
1162 .addReg(FalseReg) in insertVectorSelect()
1176 .addReg(FalseReg) in insertVectorSelect()
1190 .addReg(FalseReg) in insertVectorSelect()
1206 .addReg(FalseReg) in insertVectorSelect()
1222 .addReg(FalseReg) in insertVectorSelect()
1240 .addReg(FalseReg) in insertVectorSelect()
2851 Register FalseReg, int &CondCycles, in canInsertSelect() argument
2858 if (MRI.getRegClass(FalseReg) != RC) in canInsertSelect()
[all …]
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h903 Register TrueReg, Register FalseReg, in canInsertSelect() argument
927 Register TrueReg, Register FalseReg) const { in insertSelect() argument
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h233 Register FalseReg) const override;
H A DAArch64InstrInfo.cpp608 Register FalseReg, int &CondCycles, in canInsertSelect() argument
614 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
636 else if (canFoldIntoCSel(MRI, FalseReg)) in canInsertSelect()
658 Register TrueReg, Register FalseReg) const { in insertSelect()
766 TrueReg = FalseReg; in insertSelect()
768 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); in insertSelect()
772 FalseReg = NewVReg; in insertSelect()
781 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
786 .addReg(FalseReg) in insertSelect()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp1146 MachineOperand FalseReg = MI.getOperand(Invert ? 5 : 4); in optimizeSelect() local
1148 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
1170 NewMI.add(FalseReg); in optimizeSelect()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp5859 Register FalseReg = Sel.getFalseReg(); in matchSelectToLogical() local
5862 auto *FalseDef = getDefIgnoringCopies(FalseReg, MRI); in matchSelectToLogical()
5876 MIB.buildOr(DstReg, Cond, FalseReg); in matchSelectToLogical()
5884 if (Cond == FalseReg || (MaybeCstFalse && MaybeCstFalse->isZero())) { in matchSelectToLogical()
5902 MIB.buildAnd(DstReg, MIB.buildNot(OpTy, Cond), FalseReg); in matchSelectToLogical()