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Searched refs:DstVT (Results 1 – 25 of 35) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td2062 ValueType DstVT> {
2081 !if(!eq(DstVT.Size, 1),
2104 class getOutsDPP <bit HasDst, ValueType DstVT, RegisterOperand DstRCDPP> {
2106 !if(!eq(DstVT.Size, 1),
2113 class getOutsSDWA <bit HasDst, ValueType DstVT, RegisterOperand DstRCSDWA> {
2115 !if(!eq(DstVT.Size, 1),
2123 class getAsm32 <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
2124 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
2192 class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
2194 !if(!eq(DstVT.Size, 1),
[all …]
H A DVOPInstructions.td139 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
572 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
784 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
1034 !subst(P.DstRC, P.DstVT, tmp)));
1081 list<dag> ret3 = [(set P.DstVT:$vdst,
1086 list<dag> ret2 = [(set P.DstVT:$vdst,
1090 list<dag> ret1 = [(set P.DstVT:$vdst,
1106 list<dag> ret3 = [(set P.DstVT:$vdst,
1111 list<dag> ret2 = [(set P.DstVT:$vdst,
1116 list<dag> ret1 = [(set P.DstVT:$vdst,
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H A DVOP3PInstructions.td464 bit NoDstOverlap = !gt(DstVT.Size, 128);
471 let Src2VT = DstVT;
740 GCNPat < (P.DstVT (node
745 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, $src2_mod…
749 GCNPat < (P.DstVT (node
754 …(P.DstVT (Inst (i32 8), P.Src0VT:$src0, (i32 8), P.Src1VT:$src1, i32:$src2_modifiers, P.Src2VT:$sr…
758 GCNPat < (P.DstVT (node
763 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, (i32 8), …
H A DVOP1Instructions.td51 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
103 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
105 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
107 [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]
H A DVOP3Instructions.td109 let HasOMod = !ne(DstVT.Value, f16.Value);
771 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
772 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
773 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86FastISel.cpp86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
699 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend() argument
702 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); in X86FastEmitExtend()
1238 EVT DstVT = VA.getValVT(); in X86SelectRet() local
1240 if (SrcVT != DstVT) { in X86SelectRet()
1247 assert(DstVT == MVT::i32 && "X86 should always ext to i32"); in X86SelectRet()
1259 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); in X86SelectRet()
1536 EVT DstVT = TLI.getValueType(DL, I->getType()); in X86SelectZExt() local
1537 if (!TLI.isTypeLegal(DstVT)) in X86SelectZExt()
1555 if (DstVT == MVT::i64) { in X86SelectZExt()
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H A DX86SelectionDAGInfo.cpp248 EVT DstVT = Dst.getValueType(); in emitConstantSizeRepmov() local
252 DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)), in emitConstantSizeRepmov()
H A DX86ISelLowering.cpp6794 auto MakeBroadcastOp = [&](SDValue Op, MVT OpVT, MVT DstVT) { in getAVX512Node() argument
6802 if (OpVT == DstVT && Op.getOpcode() != ISD::BITCAST) in getAVX512Node()
6811 return DAG.getConstant(SplatValue, DL, DstVT); in getAVX512Node()
6818 MVT DstVT = VT; in getAVX512Node() local
6820 DstVT = MVT::getVectorVT(SVT, 512 / SVT.getSizeInBits()); in getAVX512Node()
6831 if (SDValue BroadcastOp = MakeBroadcastOp(Op, OpVT, DstVT)) { in getAVX512Node()
6841 SDValue Res = DAG.getNode(Opcode, DL, DstVT, SrcOps); in getAVX512Node()
12436 static bool matchShuffleAsVTRUNC(MVT &SrcVT, MVT &DstVT, MVT VT, in matchShuffleAsVTRUNC() argument
12458 DstVT = MVT::getIntegerVT(EltSizeInBits); in matchShuffleAsVTRUNC()
12461 DstVT = MVT::getVectorVT(DstVT, NumSrcElts); in matchShuffleAsVTRUNC()
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H A DX86ISelDAGToDAG.cpp1284 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1287 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1295 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1311 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
1322 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, in PreprocessISelDAG()
1340 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1343 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1351 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1367 MVT MemVT = (N->getOpcode() == ISD::STRICT_FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
1396 SDVTList VTs = CurDAG->getVTList(DstVT, MVT::Other); in PreprocessISelDAG()
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H A DX86InstrAVX512.td7489 RegisterClass SrcRC, X86VectorVTInfo DstVT,
7493 let ExeDomain = DstVT.ExeDomain, Uses = _Uses,
7496 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
7497 (ins DstVT.FRC:$src1, SrcRC:$src),
7501 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
7502 (ins DstVT.FRC:$src1, x86memop:$src),
7506 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
7507 (ins DstVT.RC:$src1, SrcRC:$src2),
7509 [(set DstVT.RC:$dst,
7510 (OpNode (DstVT.VT DstVT.RC:$src1), SrcRC:$src2))]>,
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1063 MVT DstVT; in SelectIToFP() local
1065 if (!isTypeLegal(DstTy, DstVT)) in SelectIToFP()
1068 if (DstVT != MVT::f32 && DstVT != MVT::f64) in SelectIToFP()
1089 if (DstVT == MVT::f32) in SelectIToFP()
1112 if (DstVT == MVT::f32 && !Subtarget->hasFPCVT()) in SelectIToFP()
1134 if (DstVT == MVT::f32) in SelectIToFP()
1188 MVT DstVT, SrcVT; in SelectFPToI() local
1190 if (!isTypeLegal(DstTy, DstVT)) in SelectFPToI()
1193 if (DstVT != MVT::i32 && DstVT != MVT::i64) in SelectFPToI()
1197 if (DstVT == MVT::i64 && !IsSigned && !Subtarget->hasFPCVT() && in SelectFPToI()
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/openbsd-src/gnu/llvm/llvm/lib/Transforms/Scalar/
H A DScalarizer.cpp747 auto *DstVT = dyn_cast<FixedVectorType>(BCI.getDestTy()); in visitBitCastInst() local
749 if (!DstVT || !SrcVT) in visitBitCastInst()
752 unsigned DstNumElems = DstVT->getNumElements(); in visitBitCastInst()
761 Res[I] = Builder.CreateBitCast(Op0[I], DstVT->getElementType(), in visitBitCastInst()
767 auto *MidTy = FixedVectorType::get(DstVT->getElementType(), FanOut); in visitBitCastInst()
793 Res[ResI] = Builder.CreateBitCast(V, DstVT->getElementType(), in visitBitCastInst()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1380 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectCast() local
1382 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1383 !DstVT.isSimple()) in selectCast()
1388 if (!TLI.isTypeLegal(DstVT)) in selectCast()
1400 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1418 MVT DstVT = DstEVT.getSimpleVT(); in selectBitCast() local
1424 if (SrcVT == DstVT) { in selectBitCast()
1430 Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); in selectBitCast()
1785 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectOperator() local
1786 if (DstVT.bitsGT(SrcVT)) in selectOperator()
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H A DTargetLowering.cpp676 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
677 if (SrcVT == DstVT) in SimplifyMultipleUseDemandedBits()
681 unsigned NumDstEltBits = DstVT.getScalarSizeInBits(); in SimplifyMultipleUseDemandedBits()
685 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
706 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
724 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
826 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
828 DstVT.getSizeInBits() == SrcVT.getSizeInBits() && in SimplifyMultipleUseDemandedBits()
830 return DAG.getBitcast(DstVT, Src); in SimplifyMultipleUseDemandedBits()
7713 EVT DstVT = Node->getValueType(0); in expandFP_TO_SINT() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1170 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { in isTruncateFree()
1173 if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() || in isTruncateFree()
1174 !DstVT.isInteger()) in isTruncateFree()
1177 unsigned DestBits = DstVT.getSizeInBits(); in isTruncateFree()
1196 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const { in isSExtCheaperThanZExt()
1197 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64; in isSExtCheaperThanZExt()
1961 MVT DstVT = Op.getSimpleValueType(); in lowerFP_TO_INT_SAT() local
1966 if (!DstVT.isVector()) { in lowerFP_TO_INT_SAT()
1973 if (SatVT == DstVT) in lowerFP_TO_INT_SAT()
1975 else if (DstVT == MVT::i64 && SatVT == MVT::i32) in lowerFP_TO_INT_SAT()
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H A DRISCVISelLowering.h360 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
362 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td3606 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3608 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3663 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3666 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3671 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3674 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3679 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3681 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3683 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3685 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
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H A DMipsFastISel.cpp1093 MVT DstVT, SrcVT; in selectFPToInt() local
1098 if (!isTypeLegal(DstTy, DstVT)) in selectFPToInt()
1101 if (DstVT != MVT::i32) in selectFPToInt()
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2581 static SDValue truncateVectorWithNARROW(EVT DstVT, SDValue In, const SDLoc &DL, in truncateVectorWithNARROW() argument
2586 if (SrcVT == DstVT) in truncateVectorWithNARROW()
2593 assert(DstVT.getVectorNumElements() == NumElems && "Illegal truncation"); in truncateVectorWithNARROW()
2594 assert(SrcSizeInBits > DstVT.getSizeInBits() && "Illegal truncation"); in truncateVectorWithNARROW()
2615 if (SrcVT.is256BitVector() && DstVT.is128BitVector()) { in truncateVectorWithNARROW()
2619 return DAG.getBitcast(DstVT, Res); in truncateVectorWithNARROW()
2629 return truncateVectorWithNARROW(DstVT, Res, DL, DAG); in truncateVectorWithNARROW()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1528 MVT DstVT; in SelectIToFP() local
1530 if (!isTypeLegal(Ty, DstVT)) in SelectIToFP()
1562 Register ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
1573 MVT DstVT; in SelectFPToI() local
1575 if (!isTypeLegal(RetTy, DstVT)) in SelectFPToI()
1595 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
H A DARMISelLowering.cpp6174 EVT DstVT = BC->getValueType(0); in CombineVMOVDRRCandidateWithVecOp() local
6182 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in CombineVMOVDRRCandidateWithVecOp()
6192 unsigned DstNumElt = DstVT.getVectorNumElements(); in CombineVMOVDRRCandidateWithVecOp()
6207 *DAG.getContext(), DstVT.getScalarType(), in CombineVMOVDRRCandidateWithVecOp()
6210 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, in CombineVMOVDRRCandidateWithVecOp()
6228 EVT DstVT = N->getValueType(0); in ExpandBITCAST() local
6231 (DstVT == MVT::f16 || DstVT == MVT::bf16)) in ExpandBITCAST()
6232 return MoveToHPR(SDLoc(N), DAG, MVT::i32, DstVT.getSimpleVT(), in ExpandBITCAST()
6235 if ((DstVT == MVT::i16 || DstVT == MVT::i32) && in ExpandBITCAST()
6238 ISD::TRUNCATE, SDLoc(N), DstVT, in ExpandBITCAST()
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H A DARMISelLowering.h455 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1512 EVT DstVT = N->getValueType(0); in tryIndexedLoad() local
1535 DstVT = MVT::i32; in tryIndexedLoad()
1539 if (DstVT == MVT::i64) in tryIndexedLoad()
1545 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1548 DstVT = MVT::i32; in tryIndexedLoad()
1552 if (DstVT == MVT::i64) in tryIndexedLoad()
1558 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1561 DstVT = MVT::i32; in tryIndexedLoad()
1582 SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT, in tryIndexedLoad()
H A DAArch64TargetTransformInfo.cpp2140 auto DstVT = TLI->getValueType(DL, Dst); in getExtractWithExtendCost() local
2146 if (!VecLT.second.isVector() || !TLI->isTypeLegal(DstVT)) in getExtractWithExtendCost()
2152 if (DstVT.getFixedSizeInBits() < SrcVT.getFixedSizeInBits()) in getExtractWithExtendCost()
2168 if (DstVT.getSizeInBits() != 64u || SrcVT.getSizeInBits() == 32u) in getExtractWithExtendCost()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp1388 EVT DstVT = TLI.getValueType(DL, CI->getType()); in OptimizeNoopCopyExpression() local
1391 if (SrcVT.isInteger() != DstVT.isInteger()) in OptimizeNoopCopyExpression()
1396 if (SrcVT.bitsLT(DstVT)) in OptimizeNoopCopyExpression()
1405 if (TLI.getTypeAction(CI->getContext(), DstVT) == in OptimizeNoopCopyExpression()
1407 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); in OptimizeNoopCopyExpression()
1410 if (SrcVT != DstVT) in OptimizeNoopCopyExpression()

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