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Searched refs:DefMI (Results 1 – 25 of 77) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp94 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI() local
96 if (DefMI->getParent() != MBB) in getAccDefMI()
98 if (DefMI->isCopyLike()) { in getAccDefMI()
99 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
104 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()
105 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
113 return DefMI; in getAccDefMI()
146 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard() local
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H A DARMHazardRecognizer.cpp28 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, in hasRAWHazard() argument
39 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); in hasRAWHazard()
54 MachineInstr *DefMI = LastMI; in getHazardType() local
67 DefMI = &*I; in getHazardType()
71 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && in getHazardType()
73 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) { in getHazardType()
H A DARMFixCortexA57AES1742098Pass.cpp367 MachineInstr *DefMI = *It; in analyzeMF() local
371 << printReg(MOp.getReg(), TRI) << ": " << *DefMI); in analyzeMF()
378 MachineBasicBlock::iterator DefIt = DefMI; in analyzeMF()
380 if (DefIt != DefMI->getParent()->end()) { in analyzeMF()
381 LLVM_DEBUG(dbgs() << "Moving Fixup to immediately after " << *DefMI in analyzeMF()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DTargetSchedule.cpp169 const MachineInstr *DefMI, unsigned DefOperIdx, in computeOperandLatency() argument
173 return TII->defaultDefLatency(SchedModel, *DefMI); in computeOperandLatency()
178 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx, in computeOperandLatency()
182 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
189 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI); in computeOperandLatency()
197 std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI)); in computeOperandLatency()
201 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
202 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency()
225 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() && in computeOperandLatency()
226 !DefMI->getDesc().operands()[DefOperIdx].isOptionalDef() && in computeOperandLatency()
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H A DLiveRangeEdit.cpp72 const MachineInstr *DefMI) { in checkRematerializable() argument
73 assert(DefMI && "Missing instruction"); in checkRematerializable()
75 if (!TII.isTriviallyReMaterializable(*DefMI)) in checkRematerializable()
90 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def); in scanRemattable() local
91 if (!DefMI) in scanRemattable()
93 checkRematerializable(OrigVNI, DefMI); in scanRemattable()
211 MachineInstr *DefMI = nullptr, *UseMI = nullptr; in foldAsLoad() local
217 if (DefMI && DefMI != MI) in foldAsLoad()
221 DefMI = MI; in foldAsLoad()
231 if (!DefMI || !UseMI) in foldAsLoad()
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H A DMachineTraceMetrics.cpp627 const MachineInstr *DefMI; member
631 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) in DataDep()
632 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
640 DefMI = DefI->getParent(); in DataDep()
769 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); in computeCrossBlockCriticalPath() local
771 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()]; in computeCrossBlockCriticalPath()
774 unsigned Len = LIR.Height + Cycles[DefMI].Depth; in computeCrossBlockCriticalPath()
794 BlockInfo[Dep.DefMI->getParent()->getNumber()]; in updateDepth()
799 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth; in updateDepth()
801 if (!Dep.DefMI->isTransient()) in updateDepth()
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H A DMachineLateInstrsCleanup.cpp181 for (auto [Reg, DefMI] : RegDefs[FirstPred->getNumber()]) in processBlock()
184 [&, &Reg = Reg, &DefMI = DefMI](const MachineBasicBlock *Pred) { in processBlock()
187 DefMI->isIdenticalTo(*PredDefI->second); in processBlock()
189 MBBDefs[Reg] = DefMI; in processBlock()
191 << printMBBReference(*MBB) << ": " << *DefMI;); in processBlock()
H A DPHIElimination.cpp165 MachineInstr *DefMI = MRI->getVRegDef(VirtReg); in runOnMachineFunction() local
166 if (!DefMI) in runOnMachineFunction()
177 MachineBasicBlock *DefMBB = DefMI->getParent(); in runOnMachineFunction()
201 for (MachineInstr *DefMI : ImpDefs) { in runOnMachineFunction()
202 Register DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction()
205 LIS->RemoveMachineInstrFromMaps(*DefMI); in runOnMachineFunction()
206 DefMI->eraseFromParent(); in runOnMachineFunction()
496 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerPHINode() local
497 if (DefMI->isImplicitDef()) in LowerPHINode()
498 ImpDefs.insert(DefMI); in LowerPHINode()
H A DRegisterCoalescer.cpp844 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); in removeCopyByCommutingDef() local
845 if (!DefMI) in removeCopyByCommutingDef()
847 if (!DefMI->isCommutable()) in removeCopyByCommutingDef()
851 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg()); in removeCopyByCommutingDef()
854 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in removeCopyByCommutingDef()
867 if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx)) in removeCopyByCommutingDef()
870 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); in removeCopyByCommutingDef()
895 << *DefMI); in removeCopyByCommutingDef()
899 MachineBasicBlock *MBB = DefMI->getParent(); in removeCopyByCommutingDef()
901 TII->commuteInstruction(*DefMI, false, UseOpIdx, NewDstIdx); in removeCopyByCommutingDef()
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H A DMachineCSE.cpp185 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY() local
186 if (!DefMI->isCopy()) in INITIALIZE_PASS_DEPENDENCY()
188 Register SrcReg = DefMI->getOperand(1).getReg(); in INITIALIZE_PASS_DEPENDENCY()
191 if (DefMI->getOperand(0).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
205 if (DefMI->getOperand(1).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
209 LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI); in INITIALIZE_PASS_DEPENDENCY()
220 DefMI->changeDebugValuesDefReg(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
222 DefMI->eraseFromParent(); in INITIALIZE_PASS_DEPENDENCY()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64CondBrTuning.cpp67 bool tryToTuneBranch(MachineInstr &MI, MachineInstr &DefMI);
141 MachineInstr &DefMI) { in tryToTuneBranch() argument
143 if (MI.getParent() != DefMI.getParent()) in tryToTuneBranch()
149 switch (DefMI.getOpcode()) { in tryToTuneBranch()
195 if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI)) in tryToTuneBranch()
198 LLVM_DEBUG(DefMI.print(dbgs())); in tryToTuneBranch()
202 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting, /*Is64Bit=*/false); in tryToTuneBranch()
250 if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI)) in tryToTuneBranch()
253 LLVM_DEBUG(DefMI.print(dbgs())); in tryToTuneBranch()
257 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting, /*Is64Bit=*/true); in tryToTuneBranch()
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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp351 for (auto *DefMI : List) { in chooseBestLEA() local
353 int64_t AddrDispShiftTemp = getAddrDispShift(MI, MemOpNo, *DefMI, 1); in chooseBestLEA()
365 MRI->getRegClass(DefMI->getOperand(0).getReg())) in chooseBestLEA()
372 int DistTemp = calcInstrDist(*DefMI, MI); in chooseBestLEA()
382 BestLEA = DefMI; in chooseBestLEA()
526 MachineInstr *DefMI; in removeRedundantAddrCalc() local
529 if (!chooseBestLEA(Insns->second, MI, DefMI, AddrDispShift, Dist)) in removeRedundantAddrCalc()
539 DefMI->removeFromParent(); in removeRedundantAddrCalc()
540 MBB->insert(MachineBasicBlock::iterator(&MI), DefMI); in removeRedundantAddrCalc()
541 InstrPos[DefMI] = InstrPos[&MI] - 1; in removeRedundantAddrCalc()
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H A DX86TileConfig.cpp160 for (auto &DefMI : MRI.def_instructions(R)) { in INITIALIZE_PASS_DEPENDENCY() local
161 MachineBasicBlock &MBB = *DefMI.getParent(); in INITIALIZE_PASS_DEPENDENCY()
162 if (DefMI.isMoveImmediate()) { in INITIALIZE_PASS_DEPENDENCY()
165 assert(Imm == DefMI.getOperand(1).getImm() && in INITIALIZE_PASS_DEPENDENCY()
169 Imm = DefMI.getOperand(1).getImm(); in INITIALIZE_PASS_DEPENDENCY()
182 auto Iter = DefMI.getIterator(); in INITIALIZE_PASS_DEPENDENCY()
H A DX86PreTileConfig.cpp223 MachineInstr *DefMI = MRI->getVRegDef(R); in INITIALIZE_PASS_DEPENDENCY() local
224 assert(DefMI && "R must has one define instruction"); in INITIALIZE_PASS_DEPENDENCY()
225 MachineBasicBlock *DefMBB = DefMI->getParent(); in INITIALIZE_PASS_DEPENDENCY()
226 if (DefMI->isMoveImmediate() || !DefVisited.insert(DefMI).second) in INITIALIZE_PASS_DEPENDENCY()
228 if (DefMI->isPHI()) { in INITIALIZE_PASS_DEPENDENCY()
229 for (unsigned I = 1; I < DefMI->getNumOperands(); I += 2) in INITIALIZE_PASS_DEPENDENCY()
230 if (isLoopBackEdge(DefMBB, DefMI->getOperand(I + 1).getMBB())) in INITIALIZE_PASS_DEPENDENCY()
231 RecordShape(DefMI, DefMBB); // In this case, PHI is also a shape def. in INITIALIZE_PASS_DEPENDENCY()
233 WorkList.push_back(DefMI->getOperand(I).getReg()); in INITIALIZE_PASS_DEPENDENCY()
235 RecordShape(DefMI, DefMBB); in INITIALIZE_PASS_DEPENDENCY()
H A DX86CallFrameOptimization.cpp620 MachineInstr &DefMI = *MRI->getVRegDef(Reg); in canFoldIntoRegPush() local
624 if ((DefMI.getOpcode() != X86::MOV32rm && in canFoldIntoRegPush()
625 DefMI.getOpcode() != X86::MOV64rm) || in canFoldIntoRegPush()
626 DefMI.getParent() != FrameSetup->getParent()) in canFoldIntoRegPush()
631 for (MachineBasicBlock::iterator I = DefMI; I != FrameSetup; ++I) in canFoldIntoRegPush()
635 return &DefMI; in canFoldIntoRegPush()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp280 MachineInstr *DefMI = MRI.getVRegDef(Reg); in isCallViaRegister() local
282 assert(DefMI); in isCallViaRegister()
286 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3) in isCallViaRegister()
289 unsigned Flags = DefMI->getOperand(2).getTargetFlags(); in isCallViaRegister()
295 assert(DefMI->hasOneMemOperand()); in isCallViaRegister()
296 Val = (*DefMI->memoperands_begin())->getValue(); in isCallViaRegister()
298 Val = (*DefMI->memoperands_begin())->getPseudoValue(); in isCallViaRegister()
/openbsd-src/gnu/llvm/llvm/lib/Target/BPF/
H A DBPFMIPeephole.cpp463 MachineInstr *DefMI; in eliminateTruncSeq() local
490 DefMI = MRI->getVRegDef(SrcReg); in eliminateTruncSeq()
491 if (DefMI) in eliminateTruncSeq()
497 DefMI = MRI->getVRegDef(SrcReg); in eliminateTruncSeq()
499 if (!DefMI) in eliminateTruncSeq()
513 if (DefMI->isPHI()) { in eliminateTruncSeq()
516 for (unsigned i = 1, e = DefMI->getNumOperands(); i < e; i += 2) { in eliminateTruncSeq()
517 MachineOperand &opnd = DefMI->getOperand(i); in eliminateTruncSeq()
533 } else if (!TruncSizeCompatible(TruncSize, DefMI->getOpcode())) { in eliminateTruncSeq()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp444 auto *DefMI = MRI.getVRegDef(Reg); in getDefSrcRegIgnoringCopies() local
445 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg()); in getDefSrcRegIgnoringCopies()
448 unsigned Opc = DefMI->getOpcode(); in getDefSrcRegIgnoringCopies()
450 Register SrcReg = DefMI->getOperand(1).getReg(); in getDefSrcRegIgnoringCopies()
454 DefMI = MRI.getVRegDef(SrcReg); in getDefSrcRegIgnoringCopies()
456 Opc = DefMI->getOpcode(); in getDefSrcRegIgnoringCopies()
458 return DefinitionAndSourceRegister{DefMI, DefSrcReg}; in getDefSrcRegIgnoringCopies()
477 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); in getOpcodeDef() local
478 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr; in getOpcodeDef()
638 const MachineInstr *DefMI = MRI.getVRegDef(Val); in isKnownNeverNaN() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp537 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); in simplifyCode() local
539 if (!DefMI) in simplifyCode()
542 unsigned DefOpc = DefMI->getOpcode(); in simplifyCode()
552 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); in simplifyCode()
575 Register DefReg1 = DefMI->getOperand(1).getReg(); in simplifyCode()
576 Register DefReg2 = DefMI->getOperand(2).getReg(); in simplifyCode()
577 unsigned DefImmed = DefMI->getOperand(3).getImm(); in simplifyCode()
620 .add(DefMI->getOperand(1)); in simplifyCode()
626 (DefMI->getOperand(2).getImm() == 0 || in simplifyCode()
627 DefMI->getOperand(2).getImm() == 3)) { in simplifyCode()
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H A DPPCVSXSwapRemoval.cpp620 MachineInstr* DefMI = MRI->getVRegDef(Reg); in formWebs() local
621 assert(SwapMap.find(DefMI) != SwapMap.end() && in formWebs()
623 int DefIdx = SwapMap[DefMI]; in formWebs()
631 LLVM_DEBUG(DefMI->dump()); in formWebs()
725 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs() local
726 Register DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs()
727 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs()
737 LLVM_DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
756 LLVM_DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
802 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in markSwapsForRemoval() local
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H A DPPCInstrInfo.h230 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
234 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
240 MachineInstr &DefMI) const;
244 unsigned ConstantOpNo, MachineInstr &DefMI,
259 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
264 const MachineInstr &DefMI,
269 const MachineInstr &DefMI,
442 const MachineInstr &DefMI, unsigned DefIdx,
453 const MachineInstr &DefMI, in hasLowDefLatency() argument
601 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
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H A DPPCInstrInfo.cpp169 const MachineInstr &DefMI, unsigned DefIdx, in getOperandLatency() argument
172 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, in getOperandLatency()
175 if (!DefMI.getParent()) in getOperandLatency()
178 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency()
184 &DefMI.getParent()->getParent()->getRegInfo(); in getOperandLatency()
194 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
753 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getConstantFromConstantPool() local
754 for (auto MO2 : DefMI->uses()) in getConstantFromConstantPool()
2063 bool PPCInstrInfo::onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, in onlyFoldImmediate() argument
2066 unsigned DefOpc = DefMI.getOpcode(); in onlyFoldImmediate()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp496 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI); in optimizeSelect() local
497 bool Invert = !DefMI; in optimizeSelect()
498 if (!DefMI) in optimizeSelect()
499 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI); in optimizeSelect()
500 if (!DefMI) in optimizeSelect()
512 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg); in optimizeSelect()
515 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
518 NewMI.add(DefMI->getOperand(i)); in optimizeSelect()
536 SeenMIs.erase(DefMI); in optimizeSelect()
542 if (DefMI->getParent() != MI.getParent()) in optimizeSelect()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp715 MachineInstr *DefMI = MRI->getVRegDef(MO->getReg()); in runOnMachineFunction() local
716 if (DefMI && TII->isFoldableCopy(*DefMI)) { in runOnMachineFunction()
717 const MachineOperand &Def = DefMI->getOperand(0); in runOnMachineFunction()
721 const MachineOperand &Copied = DefMI->getOperand(1); in runOnMachineFunction()
814 MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(I).getReg()); in processPHINode() local
815 if (DefMI && DefMI->isPHI()) in processPHINode()
816 PHIOperands.insert(DefMI); in processPHINode()
850 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in lowerSpecialCase() local
851 if (DefMI && DefMI->isMoveImmediate()) { in lowerSpecialCase()
852 MachineOperand SrcConst = DefMI->getOperand(AMDGPU::getNamedOperandIdx( in lowerSpecialCase()
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/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h173 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
197 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,

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