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Searched refs:CondReg (Results 1 – 20 of 20) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86FlagsCopyLowering.cpp771 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg() local
773 if (!CondReg && !InvCondReg) in getCondOrInverseInReg()
774 CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond); in getCondOrInverseInReg()
776 if (CondReg) in getCondOrInverseInReg()
777 return {CondReg, false}; in getCondOrInverseInReg()
827 unsigned &CondReg = CondRegs[Cond]; in rewriteArithmetic() local
828 if (!CondReg) in rewriteArithmetic()
829 CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond); in rewriteArithmetic()
838 .addReg(CondReg) in rewriteArithmetic()
854 unsigned CondReg; in rewriteCMov() local
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H A DX86FastISel.cpp2113 Register CondReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
2114 if (CondReg == 0) in X86FastEmitCMoveSelect()
2118 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) { in X86FastEmitCMoveSelect()
2119 unsigned KCondReg = CondReg; in X86FastEmitCMoveSelect()
2120 CondReg = createResultReg(&X86::GR32RegClass); in X86FastEmitCMoveSelect()
2122 TII.get(TargetOpcode::COPY), CondReg) in X86FastEmitCMoveSelect()
2124 CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, X86::sub_8bit); in X86FastEmitCMoveSelect()
2127 .addReg(CondReg) in X86FastEmitCMoveSelect()
2313 Register CondReg = getRegForValue(Cond); in X86FastEmitPseudoSelect() local
2314 if (CondReg == 0) in X86FastEmitPseudoSelect()
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H A DX86InstructionSelector.cpp1401 const Register CondReg = I.getOperand(0).getReg(); in selectCondBranch() local
1406 .addReg(CondReg) in selectCondBranch()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIPreEmitPeephole.cpp90 const unsigned CondReg = TRI->getVCC(); in optimizeVccBranch() local
105 if (A->modifiesRegister(CondReg, TRI)) { in optimizeVccBranch()
106 if (!A->definesRegister(CondReg, TRI) || in optimizeVccBranch()
111 ReadsCond |= A->readsRegister(CondReg, TRI); in optimizeVccBranch()
148 if (A->getOpcode() == And && SReg == CondReg && !ModifiesExec && in optimizeVccBranch()
175 if (!MI.killsRegister(CondReg, TRI)) { in optimizeVccBranch()
178 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
181 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
238 MI.removeOperand(MI.findRegisterUseOperandIdx(CondReg, false /*Kill*/, TRI)); in optimizeVccBranch()
H A DSIOptimizeExecMaskingPreRA.cpp39 MCRegister CondReg; member in __anon61e76f800111::SIOptimizeExecMaskingPreRA
132 TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, *I, *MRI, LIS); in optimizeVcndVcmpPair()
269 (CmpReg == Register(CondReg) && in optimizeVcndVcmpPair()
272 return MI.readsRegister(CondReg, TRI); in optimizeVcndVcmpPair()
388 CondReg = MCRegister::from(Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC); in runOnMachineFunction()
H A DAMDGPURegisterBankInfo.cpp844 Register CondReg; in executeInWaterfallLoop() local
907 if (!CondReg) { in executeInWaterfallLoop()
908 CondReg = CmpReg; in executeInWaterfallLoop()
910 CondReg = B.buildAnd(S1, CondReg, CmpReg).getReg(0); in executeInWaterfallLoop()
911 MRI.setRegBank(CondReg, AMDGPU::VCCRegBank); in executeInWaterfallLoop()
923 CondReg = B.buildIntrinsic(Intrinsic::amdgcn_ballot, in executeInWaterfallLoop()
926 .addReg(CondReg) in executeInWaterfallLoop()
928 MRI.setRegClass(CondReg, WaveRC); in executeInWaterfallLoop()
933 .addReg(CondReg, RegState::Kill); in executeInWaterfallLoop()
935 MRI.setSimpleHint(NewExec, CondReg); in executeInWaterfallLoop()
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H A DSIInstrInfo.cpp2768 static void preserveCondRegFlags(MachineOperand &CondReg, in preserveCondRegFlags() argument
2770 CondReg.setIsUndef(OrigCond.isUndef()); in preserveCondRegFlags()
2771 CondReg.setIsKill(OrigCond.isKill()); in preserveCondRegFlags()
2824 MachineOperand &CondReg = CondBr->getOperand(1); in insertBranch() local
2825 CondReg.setIsUndef(Cond[1].isUndef()); in insertBranch()
2826 CondReg.setIsKill(Cond[1].isKill()); in insertBranch()
5610 Register CondReg; in emitLoadSRsrcFromVGPRLoop() local
5653 if (!CondReg) // First. in emitLoadSRsrcFromVGPRLoop()
5654 CondReg = NewCondReg; in emitLoadSRsrcFromVGPRLoop()
5658 .addReg(CondReg) in emitLoadSRsrcFromVGPRLoop()
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H A DAMDGPUInstructionSelector.cpp2720 Register CondReg = CondOp.getReg(); in selectG_BRCOND() local
2732 if (!isVCC(CondReg, *MRI)) { in selectG_BRCOND()
2733 if (MRI->getType(CondReg) != LLT::scalar(32)) in selectG_BRCOND()
2744 if (!isVCmpResult(CondReg, *MRI)) { in selectG_BRCOND()
2751 .addReg(CondReg) in selectG_BRCOND()
2753 CondReg = TmpReg; in selectG_BRCOND()
2761 if (!MRI->getRegClassOrNull(CondReg)) in selectG_BRCOND()
2762 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
2765 .addReg(CondReg); in selectG_BRCOND()
H A DAMDGPUMachineCFGStructurizer.cpp1848 Register CondReg = Cond[0].getReg(); in ensureCondIsNotKilled() local
1849 for (MachineOperand &MO : MRI->use_operands(CondReg)) in ensureCondIsNotKilled()
H A DVOP3Instructions.td714 class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat<
718 (i1 CondReg)),
H A DAMDGPUISelDAGToDAG.cpp2253 Register CondReg = UseSCCBr ? AMDGPU::SCC : TRI->getVCC(); in SelectBRCOND() local
2280 SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond); in SelectBRCOND()
H A DSIISelLowering.cpp3635 Register CondReg = MRI.createVirtualRegister(BoolRC); in emitLoadM0FromVGPRLoop() local
3654 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg) in emitLoadM0FromVGPRLoop()
3662 .addReg(CondReg, RegState::Kill); in emitLoadM0FromVGPRLoop()
3664 MRI.setSimpleHint(NewExec, CondReg); in emitLoadM0FromVGPRLoop()
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp913 unsigned CondReg = in selectSelect() local
915 if (CondReg == 0) in selectSelect()
967 .addReg(CondReg); in selectSelect()
1314 unsigned CondReg = getRegForI1Value(Br->getCondition(), Br->getParent(), Not); in selectBr() local
1315 if (CondReg == 0) in selectBr()
1324 .addReg(CondReg); in selectBr()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp961 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
962 if (CondReg == 0) in selectBranch()
965 ZExtCondReg = emitIntExt(MVT::i1, CondReg, MVT::i32, true); in selectBranch()
1040 Register CondReg = getRegForValue(Cond); in selectSelect() local
1042 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect()
1049 if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true)) in selectSelect()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp774 auto CondReg = MIB.getReg(1); in selectSelect() local
775 assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) && in selectSelect()
778 .addUse(CondReg) in selectSelect()
H A DARMFastISel.cpp1610 Register CondReg = getRegForValue(I->getOperand(0)); in SelectSelect() local
1611 if (CondReg == 0) return false; in SelectSelect()
1637 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0); in SelectSelect()
1640 .addReg(CondReg) in SelectSelect()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2481 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2482 if (!CondReg) in selectBranch()
2495 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2496 if (CondReg == 0) in selectBranch()
2508 = constrainOperandRegClass(II, CondReg, II.getNumDefs()); in selectBranch()
2717 Register CondReg = getRegForValue(Cond); in selectSelect() local
2718 if (!CondReg) in selectSelect()
2766 Register CondReg = getRegForValue(Cond); in selectSelect() local
2767 if (!CondReg) in selectSelect()
2771 CondReg = constrainOperandRegClass(II, CondReg, 1); in selectSelect()
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp785 Register CondReg = createResultReg(&PPC::CRRCRegClass); in SelectBranch() local
788 CondReg, PPCPred)) in SelectBranch()
793 .addReg(CondReg) in SelectBranch()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1752 Register CondReg = I.getOperand(0).getReg(); in selectCompareBranch() local
1753 MachineInstr *CCMI = MRI.getVRegDef(CondReg); in selectCompareBranch()
1766 emitTestBit(CondReg, /*Bit = */ 0, /*IsNegative = */ true, in selectCompareBranch()
1774 MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1); in selectCompareBranch()
3380 const Register CondReg = Sel.getCondReg(); in select() local
3390 auto TstMI = MIB.buildInstr(AArch64::ANDSWri, {DeadVReg}, {CondReg}) in select()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp4891 Register CondReg = MI.getOperand(1).getReg(); in moreElementsVector() local
4893 LLT CondTy = MRI.getType(CondReg); in moreElementsVector()
4901 auto ShufSplat = MIRBuilder.buildShuffleSplat(MoreTy, CondReg); in moreElementsVector()
5496 Register CondReg = MI.getOperand(1).getReg(); in narrowScalarSelect() local
5497 LLT CondTy = MRI.getType(CondReg); in narrowScalarSelect()
5519 CondReg, Src1Regs[I], Src2Regs[I]); in narrowScalarSelect()
5525 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); in narrowScalarSelect()