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Searched refs:CCR (Results 1 – 25 of 63) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/M68k/
H A DM68kInstrControl.td95 let Uses = [CCR] in {
98 [(set i8:$dst, (MxSetCC !cast<PatLeaf>("MxCOND"#CC), CCR))]> {
106 [(store (MxSetCC !cast<PatLeaf>("MxCOND"#CC), CCR), MEMPat:$dst)]> {
163 let isBranch = 1, isTerminator = 1, Uses = [CCR] in
197 def : Pat<(MxBrCond bb:$target, !cast<PatLeaf>("MxCOND"#cc), CCR),
314 let Uses = [CCR], Defs = [CCR], isPseudo = 1 in {
319 [(set MxDRD8:$dst, (MxSetCC_C MxCONDcs, CCR))]>;
321 [(set MxDRD16:$dst, (MxSetCC_C MxCONDcs, CCR))]>;
323 [(set MxXRD32:$dst, (MxSetCC_C MxCONDcs, CCR))]>;
324 } // Uses = [CCR], Defs = [CCR], isPseudo = 1
[all …]
H A DM68kInstrBits.td60 let Defs = [CCR] in {
63 [(set CCR, (MxBtst TYPE.VT:$dst, TYPE.VT:$bitno))]> {
69 [(set CCR, (MxBtst TYPE.VT:$dst, TYPE.IPat:$bitno))]> {
76 [(set CCR, (MxBtst (TYPE.Load MEMPat:$dst), TYPE.VT:$bitno))]> {
83 [(set CCR, (MxBtst (TYPE.Load MEMPat:$dst), TYPE.IPat:$bitno))]> {
86 } // Defs = [CCR]
H A DM68kInstrArithmetic.td56 let Defs = [CCR] in {
72 [(set DST_TYPE.VT:$dst, CCR, (NODE DST_TYPE.VT:$src, SRC_TYPE.VT:$opd))]> {
92 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.VT:$opd))]> {
106 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, (TYPE.Load PAT:$opd)))]> {
133 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))]> {
148 [(set TYPE.VT:$dst, CCR, (NODE TYPE.VT:$src, TYPE.IPat:$opd))]> {
164 // FIXME MxBiArOp_FMR/FMI cannot consume CCR from MxAdd/MxSub which leads for
193 } // Defs = [CCR]
281 // operations do not produce CCR we should not match them against Mx nodes that
302 // NOTE These naturally produce CCR
[all …]
H A DM68kInstrCompiler.td57 let usesCustomInserter = 1, Uses = [CCR] in
61 (TYPE.VT (MxCmov TYPE.VT:$t, TYPE.VT:$f, imm:$cond, CCR)))]>;
76 // sub / add which can clobber CCR.
77 let Defs = [SP, CCR], Uses = [SP] in {
123 let Defs = [SP, CCR], Uses = [SP] in
H A DM68kInstrInfo.td37 /* CCR */ SDTCisVT<1, i8>,
41 // RES, CCR <- op LHS, RHS
44 /* CCR */ SDTCisVT<1, i8>,
49 // RES, CCR <- op LHS, RHS, CCR
52 /* CCR */ SDTCisVT<1, i8>,
55 /* CCR */ SDTCisSameAs<1, 4>
58 // RES1, RES2, CCR <- op LHS, RHS
62 /* CCR */ SDTCisVT<1, i8>,
68 /* CCR */ SDTCisVT<0, i8>,
76 /* CCR */ SDTCisVT<4, i8>
[all …]
H A DM68kInstrData.td105 let Defs = [CCR] in
340 // MOVE to/from SR/CCR
342 // A special care must be taken working with to/from CCR since it is basically
344 // instructions. Plus the original M68000 does not support moves from CCR. So in
345 // order to use CCR effectively one MUST use proper byte-size pseudo instructi-
355 let Defs = [CCR] in
378 /// Move from CCR
385 let Uses = [CCR] in {
403 } // let Uses = [CCR]
493 let Defs = [CCR] in {
H A DM68kInstrShiftRotate.td77 let Defs = [CCR] in {
89 } // Defs = [CCR]
H A DM68kISelLowering.cpp2001 SDValue CCR = EmitCmp(Op0, Op1, M68kCC, DL, DAG); in LowerSETCC() local
2003 DAG.getConstant(M68kCC, DL, MVT::i8), CCR); in LowerSETCC()
2953 if (mi.readsRegister(M68k::CCR)) in checkAndUpdateCCRKill()
2955 if (mi.definesRegister(M68k::CCR)) in checkAndUpdateCCRKill()
2963 if (SBB->isLiveIn(M68k::CCR)) in checkAndUpdateCCRKill()
2968 SelectItr->addRegisterKilled(M68k::CCR, TRI); in checkAndUpdateCCRKill()
3068 Jcc1MBB->addLiveIn(M68k::CCR); in EmitLoweredSelect()
3081 if (!LastCCRSUser->killsRegister(M68k::CCR) && in EmitLoweredSelect()
3083 Copy0MBB->addLiveIn(M68k::CCR); in EmitLoweredSelect()
3084 SinkMBB->addLiveIn(M68k::CCR); in EmitLoweredSelect()
[all …]
H A DM68kRegisterInfo.td76 def CCR : MxPseudoReg<"ccr">;
107 def CCRC : MxRegClass<[i8], 16, (add CCR)>;
H A DM68kInstrInfo.cpp669 bool FromCCR = SrcReg == M68k::CCR; in copyPhysReg()
671 bool ToCCR = DstReg == M68k::CCR; in copyPhysReg()
/openbsd-src/gnu/llvm/clang/lib/AST/
H A DComparisonCategories.cpp205 using CCR = ComparisonCategoryResult; in getPossibleResultsForType() typedef
206 std::vector<CCR> Values; in getPossibleResultsForType()
209 Values.push_back(IsStrong ? CCR::Equal : CCR::Equivalent); in getPossibleResultsForType()
210 Values.push_back(CCR::Less); in getPossibleResultsForType()
211 Values.push_back(CCR::Greater); in getPossibleResultsForType()
213 Values.push_back(CCR::Unordered); in getPossibleResultsForType()
/openbsd-src/gnu/llvm/clang/include/clang/AST/
H A DComparisonCategories.h154 using CCR = ComparisonCategoryResult; in makeWeakResult() local
155 if (!isStrong() && Res == CCR::Equal) in makeWeakResult()
156 return CCR::Equivalent; in makeWeakResult()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64RegisterBanks.td19 def CCRegBank : RegisterBank<"CC", [CCR]>;
H A DAArch64GenRegisterBankInfo.def217 PMI_None, // CCR
/openbsd-src/gnu/usr.bin/gcc/gcc/config/frv/
H A Dfrv-modes.def26 CC_CCRmode set CCR's to do conditional execution */
/openbsd-src/gnu/usr.bin/binutils/gas/config/
H A Dm68k-parse.h86 CCR, /* Condition code Reg */ enumerator
/openbsd-src/gnu/usr.bin/binutils-2.17/gas/config/
H A Dm68k-parse.h86 CCR, /* Condition code Reg */ enumerator
H A Dtc-h8300.c354 *mode = CCR; in parse_reg()
1086 case CCR: in get_specific()
1087 if (op_mode != CCR && in get_specific()
/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td60 def CCR : RegisterClass<"Lanai", [i32], 32, (add SR)> {
/openbsd-src/gnu/usr.bin/binutils-2.17/include/opcode/
H A Dh8300.h80 CCR = 0x4000, enumerator
1254 {O (O_ANDC, SB), AV_H8, 2, "andc", {{IMM8, CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}},
1424 …{O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ …
1426 …{O (O_LDC, SB), AV_H8, 2, "ldc", {{RS8, CCR | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, …
1428 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSIND, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | …
1430 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSPOSTINC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | …
1432 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | …
1434 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | …
1436 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, I…
1438 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, I…
[all …]
/openbsd-src/gnu/usr.bin/binutils/include/opcode/
H A Dh8300.h79 CCR = 0x4000, enumerator
1253 {O (O_ANDC, SB), AV_H8, 2, "andc", {{IMM8, CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}},
1423 …{O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ …
1425 …{O (O_LDC, SB), AV_H8, 2, "ldc", {{RS8, CCR | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, …
1427 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSIND, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | …
1429 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSPOSTINC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | …
1431 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | …
1433 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | …
1435 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, I…
1437 …{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, I…
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/M68k/AsmParser/
H A DM68kAsmParser.cpp252 case M68k::CCR: in getRegisterIndex()
494 case M68k::CCR: in checkRegisterClass()
584 RegNo = M68k::CCR; in parseRegisterName()
/openbsd-src/gnu/usr.bin/binutils-2.17/opcodes/
H A Dh8300-dis.c314 else if ((x & MODE) == CCR) in print_one_arg()
495 if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) in bfd_h8_disassemble()
/openbsd-src/gnu/usr.bin/binutils/opcodes/
H A Dh8300-dis.c344 else if ((x & MODE) == CCR)
531 if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) ||
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td296 def CCR : Rs<7, "ccr", ["s7"]>, DwarfRegNum<[151]>;
377 def S7_6 : Rss<6, "s7:6", [SSR, CCR], ["ccr:ssr"]>, DwarfRegNum<[150]>;
599 SSR, CCR, HTID, BADVA, IMASK,

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