12159047fSniklas /* m68k-parse.h -- header file for m68k assembler 2*007c2a45Smiod Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000, 3*007c2a45Smiod 2003 Free Software Foundation, Inc. 42159047fSniklas 52159047fSniklas This file is part of GAS, the GNU Assembler. 62159047fSniklas 72159047fSniklas GAS is free software; you can redistribute it and/or modify 82159047fSniklas it under the terms of the GNU General Public License as published by 92159047fSniklas the Free Software Foundation; either version 2, or (at your option) 102159047fSniklas any later version. 112159047fSniklas 122159047fSniklas GAS is distributed in the hope that it will be useful, 132159047fSniklas but WITHOUT ANY WARRANTY; without even the implied warranty of 142159047fSniklas MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 152159047fSniklas GNU General Public License for more details. 162159047fSniklas 172159047fSniklas You should have received a copy of the GNU General Public License 182159047fSniklas along with GAS; see the file COPYING. If not, write to the Free 192159047fSniklas Software Foundation, 59 Temple Place - Suite 330, Boston, MA 202159047fSniklas 02111-1307, USA. */ 212159047fSniklas 222159047fSniklas #ifndef M68K_PARSE_H 232159047fSniklas #define M68K_PARSE_H 242159047fSniklas 252159047fSniklas /* This header file defines things which are shared between the 262159047fSniklas operand parser in m68k.y and the m68k assembler proper in 272159047fSniklas tc-m68k.c. */ 282159047fSniklas 292159047fSniklas /* The various m68k registers. */ 302159047fSniklas 312159047fSniklas /* DATA and ADDR have to be contiguous, so that reg-DATA gives 322159047fSniklas 0-7==data reg, 8-15==addr reg for operands that take both types. 332159047fSniklas 342159047fSniklas We don't use forms like "ADDR0 = ADDR" here because this file is 352159047fSniklas likely to be used on an Apollo, and the broken Apollo compiler 362159047fSniklas gives an `undefined variable' error if we do that, according to 372159047fSniklas troy@cbme.unsw.edu.au. */ 382159047fSniklas 392159047fSniklas #define DATA DATA0 402159047fSniklas #define ADDR ADDR0 412159047fSniklas #define SP ADDR7 422159047fSniklas #define BAD BAD0 432159047fSniklas #define BAC BAC0 442159047fSniklas 452159047fSniklas enum m68k_register 462159047fSniklas { 472159047fSniklas DATA0 = 1, /* 1- 8 == data registers 0-7 */ 482159047fSniklas DATA1, 492159047fSniklas DATA2, 502159047fSniklas DATA3, 512159047fSniklas DATA4, 522159047fSniklas DATA5, 532159047fSniklas DATA6, 542159047fSniklas DATA7, 552159047fSniklas 562159047fSniklas ADDR0, 572159047fSniklas ADDR1, 582159047fSniklas ADDR2, 592159047fSniklas ADDR3, 602159047fSniklas ADDR4, 612159047fSniklas ADDR5, 622159047fSniklas ADDR6, 632159047fSniklas ADDR7, 642159047fSniklas 652159047fSniklas FP0, /* Eight FP registers */ 662159047fSniklas FP1, 672159047fSniklas FP2, 682159047fSniklas FP3, 692159047fSniklas FP4, 702159047fSniklas FP5, 712159047fSniklas FP6, 722159047fSniklas FP7, 732159047fSniklas 742159047fSniklas COP0, /* Co-processor #0-#7 */ 752159047fSniklas COP1, 762159047fSniklas COP2, 772159047fSniklas COP3, 782159047fSniklas COP4, 792159047fSniklas COP5, 802159047fSniklas COP6, 812159047fSniklas COP7, 822159047fSniklas 832159047fSniklas PC, /* Program counter */ 842159047fSniklas ZPC, /* Hack for Program space, but 0 addressing */ 852159047fSniklas SR, /* Status Reg */ 862159047fSniklas CCR, /* Condition code Reg */ 87b305b0f1Sespie ACC, /* Accumulator Reg */ 88b305b0f1Sespie MACSR, /* MAC Status Reg */ 89b305b0f1Sespie MASK, /* Modulus Reg */ 902159047fSniklas 912159047fSniklas /* These have to be grouped together for the movec instruction to work. */ 922159047fSniklas USP, /* User Stack Pointer */ 932159047fSniklas ISP, /* Interrupt stack pointer */ 942159047fSniklas SFC, 952159047fSniklas DFC, 962159047fSniklas CACR, 972159047fSniklas VBR, 982159047fSniklas CAAR, 992159047fSniklas MSP, 1002159047fSniklas ITT0, 1012159047fSniklas ITT1, 1022159047fSniklas DTT0, 1032159047fSniklas DTT1, 1042159047fSniklas MMUSR, 1052159047fSniklas TC, 1062159047fSniklas SRP, 1072159047fSniklas URP, 108*007c2a45Smiod BUSCR, /* 68060 added these. */ 1092159047fSniklas PCR, 110*007c2a45Smiod ROMBAR, /* mcf5200 added these. */ 1110c6d0228Sniklas RAMBAR0, 1120c6d0228Sniklas RAMBAR1, 113*007c2a45Smiod MMUBAR, /* mcfv4e added these. */ 114*007c2a45Smiod ROMBAR1, /* mcfv4e added these. */ 115*007c2a45Smiod MPCR, EDRAMBAR, SECMBAR, /* mcfv4e added these. */ 116*007c2a45Smiod PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these. */ 117*007c2a45Smiod PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these. */ 118*007c2a45Smiod PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these. */ 119*007c2a45Smiod MBAR0, MBAR1, /* mcfv4e added these. */ 120*007c2a45Smiod ACR0, ACR1, ACR2, ACR3, /* mcf5200 added these. */ 121*007c2a45Smiod FLASHBAR, RAMBAR, /* mcf528x added these. */ 1220c6d0228Sniklas MBAR, 1230c6d0228Sniklas #define last_movec_reg MBAR 124*007c2a45Smiod /* End of movec ordering constraints. */ 1252159047fSniklas 1262159047fSniklas FPI, 1272159047fSniklas FPS, 1282159047fSniklas FPC, 1292159047fSniklas 1302159047fSniklas DRP, /* 68851 or 68030 MMU regs */ 1312159047fSniklas CRP, 1322159047fSniklas CAL, 1332159047fSniklas VAL, 1342159047fSniklas SCC, 1352159047fSniklas AC, 1362159047fSniklas BAD0, 1372159047fSniklas BAD1, 1382159047fSniklas BAD2, 1392159047fSniklas BAD3, 1402159047fSniklas BAD4, 1412159047fSniklas BAD5, 1422159047fSniklas BAD6, 1432159047fSniklas BAD7, 1442159047fSniklas BAC0, 1452159047fSniklas BAC1, 1462159047fSniklas BAC2, 1472159047fSniklas BAC3, 1482159047fSniklas BAC4, 1492159047fSniklas BAC5, 1502159047fSniklas BAC6, 1512159047fSniklas BAC7, 1522159047fSniklas PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040) 1532159047fSniklas and ACUSR on 68ec030 */ 1542159047fSniklas PCSR, 1552159047fSniklas 1562159047fSniklas IC, /* instruction cache token */ 1572159047fSniklas DC, /* data cache token */ 1582159047fSniklas NC, /* no cache token */ 1592159047fSniklas BC, /* both caches token */ 1602159047fSniklas 1612159047fSniklas TT0, /* 68030 access control unit regs */ 1622159047fSniklas TT1, 1632159047fSniklas 1642159047fSniklas ZDATA0, /* suppressed data registers. */ 1652159047fSniklas ZDATA1, 1662159047fSniklas ZDATA2, 1672159047fSniklas ZDATA3, 1682159047fSniklas ZDATA4, 1692159047fSniklas ZDATA5, 1702159047fSniklas ZDATA6, 1712159047fSniklas ZDATA7, 1722159047fSniklas 1732159047fSniklas ZADDR0, /* suppressed address registers. */ 1742159047fSniklas ZADDR1, 1752159047fSniklas ZADDR2, 1762159047fSniklas ZADDR3, 1772159047fSniklas ZADDR4, 1782159047fSniklas ZADDR5, 1792159047fSniklas ZADDR6, 1802159047fSniklas ZADDR7, 181b305b0f1Sespie 182b305b0f1Sespie /* Upper and lower half of data and address registers. Order *must* 183b305b0f1Sespie be DATAxL, ADDRxL, DATAxU, ADDRxU. */ 184b305b0f1Sespie DATA0L, /* lower half of data registers */ 185b305b0f1Sespie DATA1L, 186b305b0f1Sespie DATA2L, 187b305b0f1Sespie DATA3L, 188b305b0f1Sespie DATA4L, 189b305b0f1Sespie DATA5L, 190b305b0f1Sespie DATA6L, 191b305b0f1Sespie DATA7L, 192b305b0f1Sespie 193b305b0f1Sespie ADDR0L, /* lower half of address registers */ 194b305b0f1Sespie ADDR1L, 195b305b0f1Sespie ADDR2L, 196b305b0f1Sespie ADDR3L, 197b305b0f1Sespie ADDR4L, 198b305b0f1Sespie ADDR5L, 199b305b0f1Sespie ADDR6L, 200b305b0f1Sespie ADDR7L, 201b305b0f1Sespie 202b305b0f1Sespie DATA0U, /* upper half of data registers */ 203b305b0f1Sespie DATA1U, 204b305b0f1Sespie DATA2U, 205b305b0f1Sespie DATA3U, 206b305b0f1Sespie DATA4U, 207b305b0f1Sespie DATA5U, 208b305b0f1Sespie DATA6U, 209b305b0f1Sespie DATA7U, 210b305b0f1Sespie 211b305b0f1Sespie ADDR0U, /* upper half of address registers */ 212b305b0f1Sespie ADDR1U, 213b305b0f1Sespie ADDR2U, 214b305b0f1Sespie ADDR3U, 215b305b0f1Sespie ADDR4U, 216b305b0f1Sespie ADDR5U, 217b305b0f1Sespie ADDR6U, 218b305b0f1Sespie ADDR7U, 2192159047fSniklas }; 2202159047fSniklas 2212159047fSniklas /* Size information. */ 2222159047fSniklas 2232159047fSniklas enum m68k_size 2242159047fSniklas { 2252159047fSniklas /* Unspecified. */ 2262159047fSniklas SIZE_UNSPEC, 2272159047fSniklas 2282159047fSniklas /* Byte. */ 2292159047fSniklas SIZE_BYTE, 2302159047fSniklas 2312159047fSniklas /* Word (2 bytes). */ 2322159047fSniklas SIZE_WORD, 2332159047fSniklas 2342159047fSniklas /* Longword (4 bytes). */ 2352159047fSniklas SIZE_LONG 2362159047fSniklas }; 2372159047fSniklas 2382159047fSniklas /* The structure used to hold information about an index register. */ 2392159047fSniklas 2402159047fSniklas struct m68k_indexreg 2412159047fSniklas { 2422159047fSniklas /* The index register itself. */ 2432159047fSniklas enum m68k_register reg; 2442159047fSniklas 2452159047fSniklas /* The size to use. */ 2462159047fSniklas enum m68k_size size; 2472159047fSniklas 2482159047fSniklas /* The value to scale by. */ 2492159047fSniklas int scale; 2502159047fSniklas }; 2512159047fSniklas 252191aa565Sniklas #ifdef OBJ_ELF 253191aa565Sniklas /* The type of a PIC expression. */ 254191aa565Sniklas 255191aa565Sniklas enum pic_relocation 256191aa565Sniklas { 257191aa565Sniklas pic_none, /* not pic */ 258191aa565Sniklas pic_plt_pcrel, /* @PLTPC */ 259191aa565Sniklas pic_got_pcrel, /* @GOTPC */ 260191aa565Sniklas pic_plt_off, /* @PLT */ 261191aa565Sniklas pic_got_off /* @GOT */ 262191aa565Sniklas }; 263191aa565Sniklas #endif 264191aa565Sniklas 2652159047fSniklas /* The structure used to hold information about an expression. */ 2662159047fSniklas 2672159047fSniklas struct m68k_exp 2682159047fSniklas { 2692159047fSniklas /* The size to use. */ 2702159047fSniklas enum m68k_size size; 2712159047fSniklas 272191aa565Sniklas #ifdef OBJ_ELF 273191aa565Sniklas /* The type of pic relocation if any. */ 274191aa565Sniklas enum pic_relocation pic_reloc; 275191aa565Sniklas #endif 276191aa565Sniklas 2772159047fSniklas /* The expression itself. */ 2782159047fSniklas expressionS exp; 2792159047fSniklas }; 2802159047fSniklas 2812159047fSniklas /* The operand modes. */ 2822159047fSniklas 2832159047fSniklas enum m68k_operand_type 2842159047fSniklas { 2852159047fSniklas IMMED = 1, 2862159047fSniklas ABSL, 2872159047fSniklas DREG, 2882159047fSniklas AREG, 2892159047fSniklas FPREG, 2902159047fSniklas CONTROL, 2912159047fSniklas AINDR, 2922159047fSniklas AINC, 2932159047fSniklas ADEC, 2942159047fSniklas DISP, 2952159047fSniklas BASE, 2962159047fSniklas POST, 2972159047fSniklas PRE, 2982159047fSniklas REGLST 2992159047fSniklas }; 3002159047fSniklas 3012159047fSniklas /* The structure used to hold a parsed operand. */ 3022159047fSniklas 3032159047fSniklas struct m68k_op 3042159047fSniklas { 3052159047fSniklas /* The type of operand. */ 3062159047fSniklas enum m68k_operand_type mode; 3072159047fSniklas 3082159047fSniklas /* The main register. */ 3092159047fSniklas enum m68k_register reg; 3102159047fSniklas 3112159047fSniklas /* The register mask for mode REGLST. */ 3122159047fSniklas unsigned long mask; 3132159047fSniklas 3142159047fSniklas /* An error message. */ 3152159047fSniklas const char *error; 3162159047fSniklas 3172159047fSniklas /* The index register. */ 3182159047fSniklas struct m68k_indexreg index; 3192159047fSniklas 3202159047fSniklas /* The displacement. */ 3212159047fSniklas struct m68k_exp disp; 3222159047fSniklas 3232159047fSniklas /* The outer displacement. */ 3242159047fSniklas struct m68k_exp odisp; 3252159047fSniklas }; 3262159047fSniklas 3272159047fSniklas #endif /* ! defined (M68K_PARSE_H) */ 3282159047fSniklas 3292159047fSniklas /* The parsing function. */ 3302159047fSniklas 3312159047fSniklas extern int m68k_ip_op PARAMS ((char *, struct m68k_op *)); 3322159047fSniklas 3332159047fSniklas /* Whether register prefixes are optional. */ 3342159047fSniklas extern int flag_reg_prefix_optional; 335