| /openbsd-src/gnu/llvm/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1880 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode() 1885 AM.BaseOffs%4 == 0; in isLegalAddressingMode() 1892 return isImmUs(AM.BaseOffs); in isLegalAddressingMode() 1895 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode() 1900 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode() 1903 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode() 1907 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode() 1910 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 2597 if (BaseOffs != other.BaseOffs) in compare() 2619 return !BaseOffs && !Scale && !(BaseGV && BaseReg); in isTrivial() 2633 return ConstantInt::get(IntPtrTy, BaseOffs); in GetFieldAsValue() 2670 BaseOffs = 0; in SetCombinedField() 2695 if (BaseOffs) { in print() 2696 OS << (NeedPlus ? " + " : "") << BaseOffs; in print() 4004 TestAddrMode.BaseOffs += CI->getSExtValue() * TestAddrMode.Scale; in matchScaledValue() 4052 if (AddrMode.BaseOffs) { in matchScaledValue() 4065 TestAddrMode.BaseOffs -= Offset.getLimitedValue(); in matchScaledValue() 4720 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr() [all …]
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| H A D | TargetLoweringBase.cpp | 1926 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode() 1938 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode() 1943 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUPerfHintAnalysis.cpp | 260 auto *Ptr = GetPointerBaseWithConstantOffset(GEP, AM.BaseOffs, *DL); in visit()
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| H A D | SIISelLowering.cpp | 1237 return AM.BaseOffs == 0 && AM.Scale == 0; in isLegalFlatAddressingMode() 1241 (AM.BaseOffs == 0 || in isLegalFlatAddressingMode() 1243 AM.BaseOffs, AMDGPUAS::FLAT_ADDRESS, SIInstrFlags::FLAT)); in isLegalFlatAddressingMode() 1249 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset( in isLegalGlobalAddressingMode() 1250 AM.BaseOffs, AMDGPUAS::GLOBAL_ADDRESS, in isLegalGlobalAddressingMode() 1279 if (!SIInstrInfo::isLegalMUBUFImmOffset(AM.BaseOffs)) in isLegalMUBUFAddressingMode() 1320 if (AM.BaseOffs % 4 != 0) in isLegalAddressingMode() 1332 if (!isUInt<8>(AM.BaseOffs / 4)) in isLegalAddressingMode() 1337 if (!isUInt<32>(AM.BaseOffs / 4)) in isLegalAddressingMode() 1341 if (!isUInt<20>(AM.BaseOffs)) in isLegalAddressingMode() [all …]
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| H A D | SILoadStoreOptimizer.cpp | 2175 AM.BaseOffs = Dist; in promoteConstantOffsetToImm() 2200 AM.BaseOffs = P.second - AnchorAddr.Offset; in promoteConstantOffsetToImm()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | BasicTTIImpl.h | 333 AM.BaseOffs = BaseOffset; 388 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
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| H A D | TargetLowering.h | 2594 int64_t BaseOffs = 0; member
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1392 AMNew.BaseOffs = CombinedImm.getSExtValue(); in matchPtrAddImmedChain() 1396 AMOld.BaseOffs = MaybeImm2Val->Value.getSExtValue(); in matchPtrAddImmedChain() 1406 MatchInfo.Imm = AMNew.BaseOffs; in matchPtrAddImmedChain() 4561 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern() 4573 AM.BaseOffs = CombinedValue; in reassociationCanBreakAddressingModePattern()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 3653 if (!isAligned(A, AM.BaseOffs)) in isLegalAddressingMode() 3656 if (!isInt<11>(AM.BaseOffs >> Log2(A))) in isLegalAddressingMode()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 2434 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
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| H A D | ARMISelLowering.cpp | 19435 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) in isLegalAddressingMode() 19447 if (AM.BaseOffs) in isLegalAddressingMode()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 776 if (AM.BaseOffs < 0) in isLegalAddressingMode()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1011 int64_t Offs = AM.BaseOffs; in isLegalAddressingMode()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 3397 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
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| H A D | AArch64ISelLowering.cpp | 14834 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) in isLegalAddressingMode() 14841 return AM.HasBaseReg && !AM.BaseOffs && in isLegalAddressingMode() 14856 int64_t Offset = AM.BaseOffs; in isLegalAddressingMode()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 16487 if (Ty->isVectorTy() && AM.BaseOffs != 0 && !Subtarget.hasP9Vector()) in isLegalAddressingMode() 16491 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode() 16503 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode() 16508 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 4543 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 981 if (!isInt<20>(AM.BaseOffs)) in isLegalAddressingMode() 989 if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs)) in isLegalAddressingMode()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1059 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern() 1067 AM.BaseOffs = CombinedValue; in reassociationCanBreakAddressingModePattern() 1086 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern() 2171 AM.BaseOffs = Offset->getSExtValue(); in canFoldInAddressingMode() 2180 AM.BaseOffs = -Offset->getSExtValue(); in canFoldInAddressingMode()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1129 return AM.HasBaseReg && AM.Scale == 0 && !AM.BaseOffs; in isLegalAddressingMode() 1132 if (!isInt<12>(AM.BaseOffs)) in isLegalAddressingMode()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 6672 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
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| H A D | X86ISelLowering.cpp | 34835 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr)) in isLegalAddressingMode() 34852 Subtarget.is64Bit() && (AM.BaseOffs || AM.Scale > 1)) in isLegalAddressingMode()
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