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Searched refs:ARM (Results 1 – 25 of 600) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp186 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
187 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
188 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
189 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
190 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
191 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
193 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
194 { ARM::VLD1d16QPseudoWB_fixed, ARM::VLD1d16Qwb_fixed, true, true, false, SingleSpc, 4, 4 ,false…
195 { ARM::VLD1d16QPseudoWB_register, ARM::VLD1d16Qwb_register, true, true, true, SingleSpc, 4, 4 ,fa…
196 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
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H A DARMFeatures.h28 case ARM::tADC: in isV8EligibleForIT()
29 case ARM::tADDi3: in isV8EligibleForIT()
30 case ARM::tADDi8: in isV8EligibleForIT()
31 case ARM::tADDrr: in isV8EligibleForIT()
32 case ARM::tAND: in isV8EligibleForIT()
33 case ARM::tASRri: in isV8EligibleForIT()
34 case ARM::tASRrr: in isV8EligibleForIT()
35 case ARM::tBIC: in isV8EligibleForIT()
36 case ARM::tEOR: in isV8EligibleForIT()
37 case ARM::tLSLri: in isV8EligibleForIT()
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H A DARMFixCortexA57AES1742098Pass.cpp129 return Opc == ARM::AESD || Opc == ARM::AESE; in isFirstAESPairInstr()
145 case ARM::AESD: in isSafeAESInput()
146 case ARM::AESE: in isSafeAESInput()
147 case ARM::AESMC: in isSafeAESInput()
148 case ARM::AESIMC: in isSafeAESInput()
152 case ARM::VANDd: in isSafeAESInput()
153 case ARM::VANDq: in isSafeAESInput()
154 case ARM::VORRd: in isSafeAESInput()
155 case ARM::VORRq: in isSafeAESInput()
156 case ARM::VEORd: in isSafeAESInput()
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H A DARMRegisterBankInfo.cpp30 namespace ARM { namespace
141 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
143 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()
146 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
148 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
150 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
152 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
154 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
156 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
158 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnoip_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
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H A DARMBaseInstrInfo.cpp95 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
96 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
97 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
98 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
99 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
100 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
101 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
102 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
105 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
106 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
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H A DThumb2SizeReduction.cpp84 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
85 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
86 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
87 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
88 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
89 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
90 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
91 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
92 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
95 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
[all …]
H A DThumb2InstrInfo.cpp53 return MCInstBuilder(ARM::tHINT).addImm(0).addImm(ARMCC::AL).addReg(0); in getNop()
92 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
140 get(ARM::t2CSEL), DestReg) in optimizeSelect()
155 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
158 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
178 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
179 BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
188 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
194 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass); in storeRegToStackSlot()
197 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot()
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H A DARMInstrInfo.cpp37 NopInst.setOpcode(ARM::HINT); in getNop()
42 NopInst.setOpcode(ARM::MOVr); in getNop()
43 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
56 case ARM::LDR_PRE_IMM: in getUnindexedOpcode()
57 case ARM::LDR_PRE_REG: in getUnindexedOpcode()
58 case ARM::LDR_POST_IMM: in getUnindexedOpcode()
59 case ARM::LDR_POST_REG: in getUnindexedOpcode()
60 return ARM::LDRi12; in getUnindexedOpcode()
61 case ARM::LDRH_PRE: in getUnindexedOpcode()
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H A DARMBaseInstrInfo.h370 return MI->getOpcode() == ARM::t2LoopEndDec || in isUnspillableTerminatorImpl()
371 MI->getOpcode() == ARM::t2DoLoopStartTP || in isUnspillableTerminatorImpl()
372 MI->getOpcode() == ARM::t2WhileLoopStartLR || in isUnspillableTerminatorImpl()
373 MI->getOpcode() == ARM::t2WhileLoopStartTP; in isUnspillableTerminatorImpl()
558 return MachineOperand::CreateReg(ARM::CPSR,
565 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
572 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 || in isVPTOpcode()
573 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 || in isVPTOpcode()
574 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 || in isVPTOpcode()
575 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 || in isVPTOpcode()
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H A DARMLoadStoreOptimizer.cpp211 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
222 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
226 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
227 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
228 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset()
229 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
233 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
234 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
259 case ARM::LDRi12: in getLoadStoreMultipleOpcode()
263 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
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H A DMVETailPredUtils.h30 case ARM::MVE_VCTP8: in VCTPOpcodeToLSTP()
31 return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8; in VCTPOpcodeToLSTP()
32 case ARM::MVE_VCTP16: in VCTPOpcodeToLSTP()
33 return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16; in VCTPOpcodeToLSTP()
34 case ARM::MVE_VCTP32: in VCTPOpcodeToLSTP()
35 return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32; in VCTPOpcodeToLSTP()
36 case ARM::MVE_VCTP64: in VCTPOpcodeToLSTP()
37 return IsDoLoop ? ARM::MVE_DLSTP_64 : ARM::MVE_WLSTP_64; in VCTPOpcodeToLSTP()
46 case ARM::MVE_VCTP8: in getTailPredVectorWidth()
48 case ARM::MVE_VCTP16: in getTailPredVectorWidth()
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H A DARMISelDAGToDAG.cpp121 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); in SelectCMOVPred()
521 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
1603 Opcode = ARM::LDR_PRE_IMM; in tryARMIndexedLoad()
1607 Opcode = ARM::LDR_POST_IMM; in tryARMIndexedLoad()
1611 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in tryARMIndexedLoad()
1618 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1619 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1624 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; in tryARMIndexedLoad()
1630 Opcode = ARM::LDRB_PRE_IMM; in tryARMIndexedLoad()
1634 Opcode = ARM::LDRB_POST_IMM; in tryARMIndexedLoad()
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H A DARMFrameLowering.cpp259 IsTailCallReturn = RetOpcode == ARM::TCRETURNdi || in getArgumentStackToRestore()
260 RetOpcode == ARM::TCRETURNri; in getArgumentStackToRestore()
308 case ARM::t2ADDri: // add.w r11, sp, #xx in insertSEH()
309 case ARM::t2ADDri12: // add.w r11, sp, #xx in insertSEH()
310 case ARM::t2MOVTi16: // movt r4, #xx in insertSEH()
311 case ARM::tBL: // bl __chkstk in insertSEH()
315 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
320 case ARM::t2MOVi16: { // mov(w) r4, #xx in insertSEH()
324 BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags()); in insertSEH()
333 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)).addImm(Wide).setMIFlags(Flags); in insertSEH()
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H A DARMAsmPrinter.cpp182 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) in runOnMachineFunction()
217 if(ARM::GPRPairRegClass.contains(Reg)) { in printOperand()
220 Reg = TRI->getSubReg(Reg, ARM::gsub_0); in printOperand()
291 if (!ARM::DPRRegClass.contains(*SR)) in PrintAsmOperand()
293 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg; in PrintAsmOperand()
318 if (ARM::GPRPairRegClass.contains(RegBegin)) { in PrintAsmOperand()
320 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand()
322 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); in PrintAsmOperand()
382 ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) { in PrintAsmOperand()
390 TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1); in PrintAsmOperand()
[all …]
H A DARMTargetTransformInfo.h73 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
74 ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
75 ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
76 ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
77 ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
78 ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
79 ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
80 ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
81 ARM::FeatureProfUnpredicate, ARM::FeatureSlowVGETLNi32,
82 ARM::FeatureSlowVDUP32, ARM::FeaturePreferVMOVSR,
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H A DThumb1FrameLowering.cpp79 if (ScratchReg == ARM::NoRegister) in emitPrologueEpilogueSPUpdate()
84 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg) in emitPrologueEpilogueSPUpdate()
90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP) in emitPrologueEpilogueSPUpdate()
91 .addReg(ARM::SP) in emitPrologueEpilogueSPUpdate()
99 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitPrologueEpilogueSPUpdate()
109 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitCallSPUpdate()
136 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
139 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); in eliminateCallFramePseudoInstr()
184 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
197 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
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H A DARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
65 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
66 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
67 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
75 assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64"); in f64AssignAAPCS()
116 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
117 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
153 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
155 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
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/openbsd-src/gnu/llvm/llvm/include/llvm/TargetParser/
H A DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
9 // This file provides defines to build up the ARM target parser's logic.
49 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
51 FK_NONE, ARM::AEK_NONE)
53 FK_NONE, ARM::AEK_NONE)
55 FK_NONE, ARM::AEK_NONE)
57 FK_NONE, ARM::AEK_DSP)
59 FK_NONE, ARM::AEK_DSP)
61 FK_VFPV2, ARM::AEK_DSP)
63 FK_VFPV2, ARM::AEK_DSP)
[all …]
/openbsd-src/gnu/llvm/llvm/lib/TargetParser/
H A DARMTargetParser.cpp29 ARM::ArchKind ARM::parseArch(StringRef Arch) { in parseArch()
40 unsigned ARM::parseArchVersion(StringRef Arch) { in parseArchVersion()
94 static ARM::ProfileKind getProfileKind(ARM::ArchKind AK) { in getProfileKind()
96 case ARM::ArchKind::ARMV6M: in getProfileKind()
97 case ARM::ArchKind::ARMV7M: in getProfileKind()
98 case ARM::ArchKind::ARMV7EM: in getProfileKind()
99 case ARM::ArchKind::ARMV8MMainline: in getProfileKind()
100 case ARM::ArchKind::ARMV8MBaseline: in getProfileKind()
101 case ARM::ArchKind::ARMV8_1MMainline: in getProfileKind()
102 return ARM::ProfileKind::M; in getProfileKind()
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMTargetStreamer.cpp112 void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) {} in emitArch()
114 void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) {} in emitObjectArch()
136 if (STI.hasFeature(ARM::HasV9_0aOps)) in getArchForCPU()
138 else if (STI.hasFeature(ARM::HasV8Ops)) { in getArchForCPU()
139 if (STI.hasFeature(ARM::FeatureRClass)) in getArchForCPU()
142 } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps)) in getArchForCPU()
144 else if (STI.hasFeature(ARM::HasV8MMainlineOps)) in getArchForCPU()
146 else if (STI.hasFeature(ARM::HasV7Ops)) { in getArchForCPU()
147 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP)) in getArchForCPU()
150 } else if (STI.hasFeature(ARM::HasV6T2Ops)) in getArchForCPU()
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H A DARMAsmBackend.cpp73 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
127 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
211 bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2]; in getRelaxedOpcode()
212 bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps]; in getRelaxedOpcode()
217 case ARM::tBcc: in getRelaxedOpcode()
218 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; in getRelaxedOpcode()
219 case ARM::tLDRpci: in getRelaxedOpcode()
220 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; in getRelaxedOpcode()
221 case ARM::tADR: in getRelaxedOpcode()
222 return HasThumb2 ? (unsigned)ARM::t2ADR : Op; in getRelaxedOpcode()
[all …]
H A DARMMCTargetDesc.cpp41 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMCRDeprecationInfo()
68 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMCRDeprecationInfo()
80 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMRCDeprecationInfo()
92 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && in getARMStoreDeprecationInfo()
98 if (MI.getOperand(OI).getReg() == ARM::PC) { in getARMStoreDeprecationInfo()
108 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && in getARMLoadDeprecationInfo()
118 case ARM::LR: in getARMLoadDeprecationInfo()
121 case ARM::PC: in getARMLoadDeprecationInfo()
145 ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName()); in ParseARMTriple()
146 if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic")) in ParseARMTriple()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp138 InstructionEndianness = STI.getFeatureBits()[ARM::ModeBigEndianInstructions] in ARMDisassembler()
718 case ARM::HVC: { in checkDecodedInstruction()
728 case ARM::t2ADDri: in checkDecodedInstruction()
729 case ARM::t2ADDri12: in checkDecodedInstruction()
730 case ARM::t2ADDrr: in checkDecodedInstruction()
731 case ARM::t2ADDrs: in checkDecodedInstruction()
732 case ARM::t2SUBri: in checkDecodedInstruction()
733 case ARM::t2SUBri12: in checkDecodedInstruction()
734 case ARM::t2SUBrr: in checkDecodedInstruction()
735 case ARM::t2SUBrs: in checkDecodedInstruction()
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/openbsd-src/gnu/usr.bin/clang/include/llvm/ARM/
H A DMakefile30 ARMGenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
32 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
35 ARMGenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
37 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
40 ARMGenCallingConv.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
42 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
45 ARMGenDAGISel.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
47 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
50 ARMGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td
52 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp119 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} in UnwindContext()
175 FPReg = ARM::SP; in reset()
299 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions()
356 return MRI->getSubReg(QReg, ARM::dsub_0); in getDRegFromQReg()
519 return getSTI().getFeatureBits()[ARM::ModeThumb]; in isThumb()
523 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbOne()
527 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbTwo()
531 return getSTI().getFeatureBits()[ARM::HasV4TOps]; in hasThumb()
535 return getSTI().getFeatureBits()[ARM::FeatureThumb2]; in hasThumb2()
539 return getSTI().getFeatureBits()[ARM::HasV6Ops]; in hasV6Ops()
[all …]

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