| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 90 Register TmpVGPR = AMDGPU::NoRegister;
96 Register SavedExecReg = AMDGPU::NoRegister;
130 ExecReg = AMDGPU::EXEC_LO; in SGPRSpillBuilder()
131 MovOpc = AMDGPU::S_MOV_B32; in SGPRSpillBuilder()
132 NotOpc = AMDGPU::S_NOT_B32; in SGPRSpillBuilder()
134 ExecReg = AMDGPU::EXEC; in SGPRSpillBuilder()
135 MovOpc = AMDGPU::S_MOV_B64; in SGPRSpillBuilder()
136 NotOpc = AMDGPU::S_NOT_B64; in SGPRSpillBuilder()
139 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in SGPRSpillBuilder()
140 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in SGPRSpillBuilder()
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| H A D | AMDGPUCombinerHelper.cpp | 22 case AMDGPU::G_FADD: in fnegFoldsIntoMI()
23 case AMDGPU::G_FSUB: in fnegFoldsIntoMI()
24 case AMDGPU::G_FMUL: in fnegFoldsIntoMI()
25 case AMDGPU::G_FMA: in fnegFoldsIntoMI()
26 case AMDGPU::G_FMAD: in fnegFoldsIntoMI()
27 case AMDGPU::G_FMINNUM: in fnegFoldsIntoMI()
28 case AMDGPU::G_FMAXNUM: in fnegFoldsIntoMI()
29 case AMDGPU::G_FMINNUM_IEEE: in fnegFoldsIntoMI()
30 case AMDGPU::G_FMAXNUM_IEEE: in fnegFoldsIntoMI()
31 case AMDGPU::G_FSIN: in fnegFoldsIntoMI()
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| H A D | SIInstrInfo.cpp | 42 namespace AMDGPU { namespace
65 : AMDGPUGenInstrInfo(AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN), in SIInstrInfo()
87 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName); in nodesHaveSameOperandValue()
88 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
141 case AMDGPU::S_AND_SAVEEXEC_B32: in resultDependsOnExec()
142 case AMDGPU::S_AND_SAVEEXEC_B64: in resultDependsOnExec()
144 case AMDGPU::S_AND_B32: in resultDependsOnExec()
145 case AMDGPU::S_AND_B64: in resultDependsOnExec()
146 if (!Use.readsRegister(AMDGPU::EXEC)) in resultDependsOnExec()
159 case AMDGPU::V_READFIRSTLANE_B32: in resultDependsOnExec()
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| H A D | AMDGPURegisterBankInfo.cpp | 118 if (Opc == AMDGPU::G_ANYEXT || Opc == AMDGPU::G_ZEXT || in applyBank()
119 Opc == AMDGPU::G_SEXT) { in applyBank()
126 if (SrcBank == &AMDGPU::VCCRegBank) { in applyBank()
130 assert(NewBank == &AMDGPU::VGPRRegBank); in applyBank()
135 auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1); in applyBank()
149 if (Opc == AMDGPU::G_TRUNC) { in applyBank()
152 assert(DstBank != &AMDGPU::VCCRegBank); in applyBank()
167 assert(NewBank == &AMDGPU::VGPRRegBank && in applyBank()
169 assert((MI.getOpcode() != AMDGPU::G_TRUNC && in applyBank()
170 MI.getOpcode() != AMDGPU::G_ANYEXT) && in applyBank()
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| H A D | AMDGPUResourceUsageAnalysis.cpp | 39 using namespace llvm::AMDGPU;
92 return AMDGPU::getTotalNumVGPRs(ST.hasGFX90AInsts(), ArgNumAGPR, ArgNumVGPR); in getTotalNumVGPRs()
114 if (AMDGPU::getAmdhsaCodeObjectVersion() >= 5) { in runOnModule()
175 Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) || in analyzeResourceUsage()
176 MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI) || in analyzeResourceUsage()
187 (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) && in analyzeResourceUsage()
188 !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) && in analyzeResourceUsage()
189 !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) { in analyzeResourceUsage()
204 MRI.isPhysRegUsed(AMDGPU::VCC_LO) || MRI.isPhysRegUsed(AMDGPU::VCC_HI); in analyzeResourceUsage()
210 MCPhysReg HighestVGPRReg = AMDGPU::NoRegister; in analyzeResourceUsage()
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| H A D | SILoadStoreOptimizer.cpp | 321 return AMDGPU::getMUBUFElements(Opc); in getOpcodeWidth()
325 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
329 return AMDGPU::getMTBUFElements(Opc); in getOpcodeWidth()
333 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getOpcodeWidth()
334 case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR: in getOpcodeWidth()
335 case AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM: in getOpcodeWidth()
336 case AMDGPU::S_LOAD_DWORD_IMM: in getOpcodeWidth()
337 case AMDGPU::GLOBAL_LOAD_DWORD: in getOpcodeWidth()
338 case AMDGPU::GLOBAL_LOAD_DWORD_SADDR: in getOpcodeWidth()
339 case AMDGPU::GLOBAL_STORE_DWORD: in getOpcodeWidth()
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| H A D | SIOptimizeExecMasking.cpp | 95 case AMDGPU::COPY: in isCopyFromExec()
96 case AMDGPU::S_MOV_B64: in isCopyFromExec()
97 case AMDGPU::S_MOV_B64_term: in isCopyFromExec()
98 case AMDGPU::S_MOV_B32: in isCopyFromExec()
99 case AMDGPU::S_MOV_B32_term: { in isCopyFromExec()
106 return AMDGPU::NoRegister; in isCopyFromExec()
112 case AMDGPU::COPY: in isCopyToExec()
113 case AMDGPU::S_MOV_B64: in isCopyToExec()
114 case AMDGPU::S_MOV_B32: { in isCopyToExec()
120 case AMDGPU::S_MOV_B64_term: in isCopyToExec()
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| H A D | GCNDPPCombine.cpp | 128 if (AMDGPU::isTrue16Inst(Op)) in isShrinkable()
130 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
140 if (!hasNoImmOrEqual(MI, AMDGPU::OpName::src0_modifiers, 0, Mask) || in isShrinkable()
141 !hasNoImmOrEqual(MI, AMDGPU::OpName::src1_modifiers, 0, Mask) || in isShrinkable()
142 !hasNoImmOrEqual(MI, AMDGPU::OpName::clamp, 0) || in isShrinkable()
143 !hasNoImmOrEqual(MI, AMDGPU::OpName::omod, 0)) { in isShrinkable()
151 int DPP32 = AMDGPU::getDPPOp32(Op); in getDPPOp()
154 int E32 = AMDGPU::getVOPe32(Op); in getDPPOp()
155 DPP32 = (E32 == -1) ? -1 : AMDGPU::getDPPOp32(E32); in getDPPOp()
161 DPP64 = AMDGPU::getDPPOp64(Op); in getDPPOp()
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| H A D | SIPeepholeSDWA.cpp | 113 using namespace AMDGPU::SDWA;
309 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
310 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) { in getSrcMods()
313 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { in getSrcMods()
314 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers)) { in getSrcMods()
344 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
345 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel); in convertToSDWA()
347 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers); in convertToSDWA()
351 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in convertToSDWA()
352 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); in convertToSDWA()
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| H A D | AMDGPUSubtarget.cpp | 118 ToggleFeature(AMDGPU::FeatureFlatForGlobal); in initializeSubtargetDependencies()
124 ToggleFeature(AMDGPU::FeatureFlatForGlobal); in initializeSubtargetDependencies()
146 if (AMDGPU::isGFX10Plus(*this) && in initializeSubtargetDependencies()
147 !getFeatureBits().test(AMDGPU::FeatureCuMode)) in initializeSubtargetDependencies()
181 MaxWavesPerEU = AMDGPU::IsaInfo::getMaxWavesPerEU(this); in GCNSubtarget()
182 EUsPerCU = AMDGPU::IsaInfo::getEUsPerCU(this); in GCNSubtarget()
196 case AMDGPU::V_LSHLREV_B64_e64: in getConstantBusLimit()
197 case AMDGPU::V_LSHLREV_B64_gfx10: in getConstantBusLimit()
198 case AMDGPU::V_LSHLREV_B64_e64_gfx11: in getConstantBusLimit()
199 case AMDGPU::V_LSHL_B64_e64: in getConstantBusLimit()
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| H A D | SIShrinkInstructions.cpp | 94 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in foldImmediates()
154 if (AMDGPU::VGPR_32RegClass.contains(Reg) && in shouldShrinkTrue16()
155 !AMDGPU::VGPR_32_Lo128RegClass.contains(Reg)) in shouldShrinkTrue16()
231 int SOPKOpc = AMDGPU::getSOPKOp(MI.getOpcode()); in shrinkScalarCompare()
237 if (SOPKOpc == AMDGPU::S_CMPK_EQ_U32 || SOPKOpc == AMDGPU::S_CMPK_LG_U32) { in shrinkScalarCompare()
241 SOPKOpc = (SOPKOpc == AMDGPU::S_CMPK_EQ_U32) ? in shrinkScalarCompare()
242 AMDGPU::S_CMPK_EQ_I32 : AMDGPU::S_CMPK_LG_I32; in shrinkScalarCompare()
261 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); in shrinkMIMG()
267 case AMDGPU::MIMGEncGfx10NSA: in shrinkMIMG()
268 NewEncoding = AMDGPU::MIMGEncGfx10Default; in shrinkMIMG()
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| H A D | SIFoldOperands.cpp | 144 case AMDGPU::V_MAC_F32_e64: in macToMad()
145 return AMDGPU::V_MAD_F32_e64; in macToMad()
146 case AMDGPU::V_MAC_F16_e64: in macToMad()
147 return AMDGPU::V_MAD_F16_e64; in macToMad()
148 case AMDGPU::V_FMAC_F32_e64: in macToMad()
149 return AMDGPU::V_FMA_F32_e64; in macToMad()
150 case AMDGPU::V_FMAC_F16_e64: in macToMad()
151 return AMDGPU::V_FMA_F16_gfx9_e64; in macToMad()
152 case AMDGPU::V_FMAC_F16_t16_e64: in macToMad()
153 return AMDGPU::V_FMA_F16_gfx9_e64; in macToMad()
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| H A D | AMDGPUInstructionSelector.cpp | 88 return MRI.getVRegDef(Reg)->getOpcode() != AMDGPU::G_TRUNC && in isVCC()
93 return RB->getID() == AMDGPU::VCCRegBankID; in isVCC()
100 MI.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in constrainCopyLikeIntrin()
131 if (SrcReg == AMDGPU::SCC) { in selectCOPY()
151 STI.isWave64() ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32; in selectCOPY()
162 TRI.isSGPRClass(SrcRC) ? AMDGPU::S_AND_B32 : AMDGPU::V_AND_B32_e32; in selectCOPY()
166 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg) in selectCOPY()
248 BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg) in getSubOperand64()
264 case AMDGPU::sub0: in getSubOperand64()
266 case AMDGPU::sub1: in getSubOperand64()
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| H A D | GCNHazardRecognizer.cpp | 62 MaxLookAhead = MF.getRegInfo().isPhysRegUsed(AMDGPU::AGPR0) ? 19 : 5; in GCNHazardRecognizer()
80 return Opcode == AMDGPU::V_DIV_FMAS_F32_e64 || Opcode == AMDGPU::V_DIV_FMAS_F64_e64; in isDivFMas()
84 return Opcode == AMDGPU::S_GETREG_B32; in isSGetReg()
89 case AMDGPU::S_SETREG_B32: in isSSetReg()
90 case AMDGPU::S_SETREG_B32_mode: in isSSetReg()
91 case AMDGPU::S_SETREG_IMM32_B32: in isSSetReg()
92 case AMDGPU::S_SETREG_IMM32_B32_mode: in isSSetReg()
99 return Opcode == AMDGPU::V_READLANE_B32 || Opcode == AMDGPU::V_WRITELANE_B32; in isRWLane()
103 return Opcode == AMDGPU::S_RFE_B64; in isRFE()
108 case AMDGPU::S_MOVRELS_B32: in isSMovRel()
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| H A D | AMDGPUArgumentUsageInfo.cpp | 95 &AMDGPU::SGPR_128RegClass, LLT::fixed_vector(4, 32)); in getPreloadedValue()
99 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
103 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
106 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
109 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
112 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
116 &AMDGPU::SGPR_32RegClass, LLT::scalar(32)); in getPreloadedValue()
119 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
123 &AMDGPU::SGPR_64RegClass, in getPreloadedValue()
127 &AMDGPU::SGPR_64RegClass, LLT::scalar(64)); in getPreloadedValue()
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| H A D | SIInsertWaitcnts.cpp | 153 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Inst.getOpcode()); in getVmemType()
154 const AMDGPU::MIMGBaseOpcodeInfo *BaseInfo = in getVmemType()
155 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in getVmemType()
160 void addWait(AMDGPU::Waitcnt &Wait, InstCounterType T, unsigned Count) { in addWait()
247 void simplifyWaitcnt(AMDGPU::Waitcnt &Wait) const;
249 void determineWait(InstCounterType T, int RegNo, AMDGPU::Waitcnt &Wait) const;
250 void applyWaitcnt(const AMDGPU::Waitcnt &Wait);
366 AMDGPU::IsaVersion IV;
421 AMDGPU::Waitcnt allZeroWaitcnt() const { in allZeroWaitcnt()
422 return AMDGPU::Waitcnt::allZero(ST->hasVscnt()); in allZeroWaitcnt()
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| H A D | SIPreAllocateWWMRegs.cpp | 166 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::ENTER_STRICT_WQM || in printWWMInfo()
167 Opc == AMDGPU::ENTER_PSEUDO_WM) { in printWWMInfo()
170 assert(Opc == AMDGPU::EXIT_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WQM || in printWWMInfo()
171 Opc == AMDGPU::EXIT_PSEUDO_WM); in printWWMInfo()
175 if (Opc == AMDGPU::ENTER_STRICT_WWM || Opc == AMDGPU::EXIT_STRICT_WWM) { in printWWMInfo()
177 } else if (Opc == AMDGPU::ENTER_PSEUDO_WM || Opc == AMDGPU::EXIT_PSEUDO_WM) { in printWWMInfo()
180 assert(Opc == AMDGPU::ENTER_STRICT_WQM || Opc == AMDGPU::EXIT_STRICT_WQM); in printWWMInfo()
216 if (MI.getOpcode() == AMDGPU::V_SET_INACTIVE_B32 || in runOnMachineFunction()
217 MI.getOpcode() == AMDGPU::V_SET_INACTIVE_B64) in runOnMachineFunction()
220 if (MI.getOpcode() == AMDGPU::ENTER_STRICT_WWM || in runOnMachineFunction()
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| H A D | AMDGPUGenRegisterBankInfo.def | 14 namespace AMDGPU {
195 if (BankID == AMDGPU::VCCRegBankID)
198 Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1;
202 case AMDGPU::VGPRRegBankID:
205 case AMDGPU::SGPRRegBankID:
208 case AMDGPU::AGPRRegBankID:
216 case AMDGPU::VGPRRegBankID:
219 case AMDGPU::SGPRRegBankID:
222 case AMDGPU::AGPRRegBankID:
230 case AMDGPU::VGPRRegBankID:
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/MCA/ |
| H A D | AMDGPUCustomBehaviour.cpp | 27 case AMDGPU::S_WAITCNT: in postProcessInstruction()
28 case AMDGPU::S_WAITCNT_EXPCNT: in postProcessInstruction()
29 case AMDGPU::S_WAITCNT_LGKMCNT: in postProcessInstruction()
30 case AMDGPU::S_WAITCNT_VMCNT: in postProcessInstruction()
31 case AMDGPU::S_WAITCNT_VSCNT: in postProcessInstruction()
32 case AMDGPU::S_WAITCNT_EXPCNT_gfx10: in postProcessInstruction()
33 case AMDGPU::S_WAITCNT_LGKMCNT_gfx10: in postProcessInstruction()
34 case AMDGPU::S_WAITCNT_VMCNT_gfx10: in postProcessInstruction()
35 case AMDGPU::S_WAITCNT_VSCNT_gfx10: in postProcessInstruction()
36 case AMDGPU::S_WAITCNT_gfx10: in postProcessInstruction()
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| /openbsd-src/gnu/usr.bin/clang/include/llvm/AMDGPU/ |
| H A D | Makefile | 48 AMDGPUGenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
50 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
52 AMDGPUGenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
54 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
56 AMDGPUGenCallingConv.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
58 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
60 AMDGPUGenDAGISel.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
62 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
64 AMDGPUGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
66 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | SIMCCodeEmitter.cpp | 143 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in getLit16Encoding()
179 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in getLit32Encoding()
215 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in getLit64Encoding()
243 case AMDGPU::OPERAND_REG_IMM_INT32: in getLitEncoding()
244 case AMDGPU::OPERAND_REG_IMM_FP32: in getLitEncoding()
245 case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: in getLitEncoding()
246 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in getLitEncoding()
247 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in getLitEncoding()
248 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in getLitEncoding()
249 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in getLitEncoding()
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| H A D | AMDGPUInstPrinter.cpp | 25 using namespace llvm::AMDGPU;
147 if (AMDGPU::isGFX10(STI)) { in printFlatOffset()
208 O << ((AMDGPU::isGFX940(STI) && in printCPol()
212 O << (AMDGPU::isGFX940(STI) ? " nt" : " slc"); in printCPol()
213 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI)) in printCPol()
215 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI)) in printCPol()
216 O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc"); in printCPol()
243 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in printDim()
262 if (STI.hasFeature(AMDGPU::FeatureR128A16)) in printR128A16()
303 using namespace llvm::AMDGPU::MTBUFFormat; in printSymbolicFormat()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
43 : AMDGPU::EncValues::SGPR_MAX_SI)
54 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) in AMDGPUDisassembler()
68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); in insertNamedMCOperand()
310 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); in IsAGPROperand()
312 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; in IsAGPROperand()
329 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 in decodeOperand_AVLdSt_Any()
330 : AMDGPU::OpName::vdata; in decodeOperand_AVLdSt_Any()
332 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); in decodeOperand_AVLdSt_Any()
334 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); in decodeOperand_AVLdSt_Any()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 44 using namespace llvm::AMDGPU;
273 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16); in isRegOrImmWithInt16InputMods()
277 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32); in isRegOrImmWithInt32InputMods()
281 return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i16); in isRegOrInlineImmWithInt16InputMods()
285 return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i32); in isRegOrInlineImmWithInt32InputMods()
289 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64); in isRegOrImmWithInt64InputMods()
293 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16); in isRegOrImmWithFP16InputMods()
297 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32); in isRegOrImmWithFP32InputMods()
301 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64); in isRegOrImmWithFP64InputMods()
305 return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f16); in isRegOrInlineImmWithFP16InputMods()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 99 namespace AMDGPU { namespace
160 return AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET; in getMultigridSyncArgImplicitArgPosition()
177 return AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET; in getHostcallImplicitArgPosition()
192 return AMDGPU::ImplicitArg::DEFAULT_QUEUE_OFFSET; in getDefaultQueueImplicitArgPosition()
204 return AMDGPU::ImplicitArg::COMPLETION_ACTION_OFFSET; in getCompletionActionImplicitArgPosition()
458 return AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0X); in isVOPD()
462 return Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || in isMAC()
463 Opc == AMDGPU::V_MAC_F32_e64_gfx10 || in isMAC()
464 Opc == AMDGPU::V_MAC_F32_e64_vi || in isMAC()
465 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || in isMAC()
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