Lines Matching refs:AMDGPU
128 if (AMDGPU::isTrue16Inst(Op)) in isShrinkable()
130 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
140 if (!hasNoImmOrEqual(MI, AMDGPU::OpName::src0_modifiers, 0, Mask) || in isShrinkable()
141 !hasNoImmOrEqual(MI, AMDGPU::OpName::src1_modifiers, 0, Mask) || in isShrinkable()
142 !hasNoImmOrEqual(MI, AMDGPU::OpName::clamp, 0) || in isShrinkable()
143 !hasNoImmOrEqual(MI, AMDGPU::OpName::omod, 0)) { in isShrinkable()
151 int DPP32 = AMDGPU::getDPPOp32(Op); in getDPPOp()
154 int E32 = AMDGPU::getVOPe32(Op); in getDPPOp()
155 DPP32 = (E32 == -1) ? -1 : AMDGPU::getDPPOp32(E32); in getDPPOp()
161 DPP64 = AMDGPU::getDPPOp64(Op); in getDPPOp()
178 case AMDGPU::IMPLICIT_DEF: in getOldOpndValue()
180 case AMDGPU::COPY: in getOldOpndValue()
181 case AMDGPU::V_MOV_B32_e32: in getOldOpndValue()
182 case AMDGPU::V_MOV_B64_PSEUDO: in getOldOpndValue()
183 case AMDGPU::V_MOV_B64_e32: in getOldOpndValue()
184 case AMDGPU::V_MOV_B64_e64: { in getOldOpndValue()
199 assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp || in createDPPInst()
200 MovMI.getOpcode() == AMDGPU::V_MOV_B64_dpp || in createDPPInst()
201 MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO); in createDPPInst()
210 int OrigOpE32 = AMDGPU::getVOPe32(OrigOp); in createDPPInst()
212 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); in createDPPInst()
214 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); in createDPPInst()
231 if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) { in createDPPInst()
235 if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) { in createDPPInst()
243 const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old); in createDPPInst()
249 TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()), in createDPPInst()
268 AMDGPU::OpName::src0_modifiers)) { in createDPPInst()
269 assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp, in createDPPInst()
270 AMDGPU::OpName::src0_modifiers)); in createDPPInst()
275 } else if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::src0_modifiers)) { in createDPPInst()
279 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst()
291 AMDGPU::OpName::src1_modifiers)) { in createDPPInst()
292 assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp, in createDPPInst()
293 AMDGPU::OpName::src1_modifiers)); in createDPPInst()
298 } else if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::src1_modifiers)) { in createDPPInst()
302 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
313 TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2_modifiers)) { in createDPPInst()
315 AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::src2_modifiers)); in createDPPInst()
321 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in createDPPInst()
323 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || in createDPPInst()
333 auto *ClampOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::clamp); in createDPPInst()
334 if (ClampOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::clamp)) { in createDPPInst()
337 auto *VdstInOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst_in); in createDPPInst()
339 AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::vdst_in)) { in createDPPInst()
342 auto *OmodOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::omod); in createDPPInst()
343 if (OmodOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::omod)) { in createDPPInst()
349 TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel)) { in createDPPInst()
356 if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::op_sel)) in createDPPInst()
360 TII->getNamedOperand(OrigMI, AMDGPU::OpName::op_sel_hi)) { in createDPPInst()
370 if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::op_sel_hi)) in createDPPInst()
373 auto *NegOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_lo); in createDPPInst()
374 if (NegOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::neg_lo)) { in createDPPInst()
377 auto *NegHiOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_hi); in createDPPInst()
378 if (NegHiOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::neg_hi)) { in createDPPInst()
382 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl)); in createDPPInst()
383 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask)); in createDPPInst()
384 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask)); in createDPPInst()
400 case AMDGPU::V_ADD_U32_e32: in isIdentityValue()
401 case AMDGPU::V_ADD_U32_e64: in isIdentityValue()
402 case AMDGPU::V_ADD_CO_U32_e32: in isIdentityValue()
403 case AMDGPU::V_ADD_CO_U32_e64: in isIdentityValue()
404 case AMDGPU::V_OR_B32_e32: in isIdentityValue()
405 case AMDGPU::V_OR_B32_e64: in isIdentityValue()
406 case AMDGPU::V_SUBREV_U32_e32: in isIdentityValue()
407 case AMDGPU::V_SUBREV_U32_e64: in isIdentityValue()
408 case AMDGPU::V_SUBREV_CO_U32_e32: in isIdentityValue()
409 case AMDGPU::V_SUBREV_CO_U32_e64: in isIdentityValue()
410 case AMDGPU::V_MAX_U32_e32: in isIdentityValue()
411 case AMDGPU::V_MAX_U32_e64: in isIdentityValue()
412 case AMDGPU::V_XOR_B32_e32: in isIdentityValue()
413 case AMDGPU::V_XOR_B32_e64: in isIdentityValue()
417 case AMDGPU::V_AND_B32_e32: in isIdentityValue()
418 case AMDGPU::V_AND_B32_e64: in isIdentityValue()
419 case AMDGPU::V_MIN_U32_e32: in isIdentityValue()
420 case AMDGPU::V_MIN_U32_e64: in isIdentityValue()
425 case AMDGPU::V_MIN_I32_e32: in isIdentityValue()
426 case AMDGPU::V_MIN_I32_e64: in isIdentityValue()
431 case AMDGPU::V_MAX_I32_e32: in isIdentityValue()
432 case AMDGPU::V_MAX_I32_e64: in isIdentityValue()
437 case AMDGPU::V_MUL_I32_I24_e32: in isIdentityValue()
438 case AMDGPU::V_MUL_I32_I24_e64: in isIdentityValue()
439 case AMDGPU::V_MUL_U32_U24_e32: in isIdentityValue()
440 case AMDGPU::V_MUL_U32_U24_e64: in isIdentityValue()
453 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
463 auto MovDst = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst); in createDPPInst()
486 assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp || in combineDPPMov()
487 MovMI.getOpcode() == AMDGPU::V_MOV_B64_dpp || in combineDPPMov()
488 MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO); in combineDPPMov()
491 auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst); in combineDPPMov()
504 if (MovMI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO || in combineDPPMov()
505 MovMI.getOpcode() == AMDGPU::V_MOV_B64_dpp) { in combineDPPMov()
506 auto *DppCtrl = TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl); in combineDPPMov()
508 if (!AMDGPU::isLegal64BitDPPControl(DppCtrl->getImm())) { in combineDPPMov()
516 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); in combineDPPMov()
518 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); in combineDPPMov()
523 auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl); in combineDPPMov()
527 auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old); in combineDPPMov()
528 auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in combineDPPMov()
582 TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg); in combineDPPMov()
602 assert((TII->get(OrigOp).getSize() != 4 || !AMDGPU::isTrue16Inst(OrigOp)) && in combineDPPMov()
604 if (OrigOp == AMDGPU::REG_SEQUENCE) { in combineDPPMov()
642 if (OrigMI.modifiesRegister(AMDGPU::EXEC, ST->getRegisterInfo())) { in combineDPPMov()
647 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0); in combineDPPMov()
648 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in combineDPPMov()
654 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); in combineDPPMov()
726 if (MI.getOpcode() == AMDGPU::V_MOV_B32_dpp && combineDPPMov(MI)) { in runOnMachineFunction()
729 } else if (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO || in runOnMachineFunction()
730 MI.getOpcode() == AMDGPU::V_MOV_B64_dpp) { in runOnMachineFunction()