Searched refs:variadicOpsAreDefs (Results 1 – 16 of 16) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrCall.td | 41 let variadicOpsAreDefs = 1, usesCustomInserter = 1, isPseudo = 1 in
46 let variadicOpsAreDefs = 1, usesCustomInserter = 1, isPseudo = 1 in
54 let variadicOpsAreDefs = 1 in
60 let variadicOpsAreDefs = 1 in
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| H A D | WebAssemblyMCInstLower.cpp | 345 else if (Desc.variadicOpsAreDefs()) in lower()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| H A D | WebAssemblyInstPrinter.cpp | 86 Desc.variadicOpsAreDefs()) in printInst()
90 if (Desc.variadicOpsAreDefs()) { in printInst()
95 bool NeedsComma = Desc.getNumOperands() > 0 && !Desc.variadicOpsAreDefs(); in printInst()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/ |
| H A D | MCInstrDesc.cpp | 48 if (variadicOpsAreDefs()) in hasDefOfPhysReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | InstrDocsEmitter.cpp | 140 FLAG(variadicOpsAreDefs) in EmitInstrDocs()
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| H A D | CodeGenInstruction.h | 281 bool variadicOpsAreDefs : 1; variable
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| H A D | CodeGenInstruction.cpp | 402 variadicOpsAreDefs = R->getValueAsBit("variadicOpsAreDefs"); in CodeGenInstruction()
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| H A D | InstrInfoEmitter.cpp | 984 if (Inst.variadicOpsAreDefs) OS << "|(1ULL<<MCID::VariadicOpsAreDefs)"; in emitRecord()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 409 bool variadicOpsAreDefs() const { in variadicOpsAreDefs() function
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 202 II.isVariadic() && II.variadicOpsAreDefs(); in CreateVirtualRegisters()
926 II.isVariadic() && II.variadicOpsAreDefs(); in EmitMachineNode()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMInstrThumb.td | 825 let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
871 variadicOpsAreDefs = 1 in
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| H A D | ARMInstrThumb2.td | 2038 let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
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| H A D | ARMInstrInfo.td | 3526 let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 1803 if (MO->isDef() && !MCOI.isOptionalDef() && !MCID.variadicOpsAreDefs()) in visitMachineOperand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | Target.td | 566 bit variadicOpsAreDefs = false; // Are variadic operands definitions?
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/TableGen/ |
| H A D | ProgRef.rst | 1933 bit variadicOpsAreDefs = 0;
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