Home
last modified time | relevance | path

Searched refs:post_div (Results 1 – 25 of 36) sorted by relevance

12

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_pll.c90 static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, in amdgpu_pll_get_fb_ref_div() argument
95 ref_div_max = min(128 / post_div, ref_div_max); in amdgpu_pll_get_fb_ref_div()
98 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); in amdgpu_pll_get_fb_ref_div()
99 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in amdgpu_pll_get_fb_ref_div()
133 unsigned post_div_min, post_div_max, post_div; in amdgpu_pll_compute() local
161 post_div_min = pll->post_div; in amdgpu_pll_compute()
162 post_div_max = pll->post_div; in amdgpu_pll_compute()
206 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { in amdgpu_pll_compute()
208 amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, in amdgpu_pll_compute()
211 (ref_div * post_div)); in amdgpu_pll_compute()
[all …]
H A Damdgpu_atombios_crtc.c591 u32 post_div, in amdgpu_atombios_crtc_program_pll() argument
618 args.v1.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
628 args.v2.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
638 args.v3.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
655 args.v5.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
685 args.v6.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
832 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in amdgpu_atombios_crtc_set_pll() local
858 pll->post_div = amdgpu_crtc->pll_post_div; in amdgpu_atombios_crtc_set_pll()
861 &fb_div, &frac_fb_div, &ref_div, &post_div); in amdgpu_atombios_crtc_set_pll()
868 ref_div, fb_div, frac_fb_div, post_div, in amdgpu_atombios_crtc_set_pll()
H A Damdgpu_atombios.h30 u32 post_div; member
70 u32 post_div; member
H A Datombios_crtc.h53 u32 post_div,
H A Damdgpu_atombios.c1030 dividers->post_div = args.v3.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1050 dividers->post_div = args.v5.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1068 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1082 dividers->post_div = args.v6_out.ucPllPostDiv; in amdgpu_atombios_get_clock_dividers()
1122 mpll_param->post_div = args.ucPostDiv; in amdgpu_atombios_get_memory_pll_dividers()
H A Damdgpu_kv_dpm.c678 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
937 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
943 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
1005 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
1068 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
1127 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
H A Damdgpu_mode.h198 uint32_t post_div; member
/netbsd-src/sys/arch/mips/atheros/
H A Dar9344.c123 uint32_t out_div, ref_div, nint, post_div; in ar9344_get_freqs() local
162 post_div = __SHIFTOUT(clk_ctl, in ar9344_get_freqs()
165 freqs->freq_bus = ddr_pll_freq / (post_div + 1); in ar9344_get_freqs()
167 freqs->freq_bus = cpu_pll_freq / (post_div + 1); in ar9344_get_freqs()
170 post_div = __SHIFTOUT(clk_ctl, in ar9344_get_freqs()
173 freqs->freq_cpu = cpu_pll_freq / (post_div + 1); in ar9344_get_freqs()
176 freqs->freq_cpu = ddr_pll_freq / (post_div + 1); in ar9344_get_freqs()
180 post_div = __SHIFTOUT(clk_ctl, in ar9344_get_freqs()
183 freqs->freq_mem = ddr_pll_freq / (post_div + 1); in ar9344_get_freqs()
185 freqs->freq_mem = cpu_pll_freq / (post_div + 1); in ar9344_get_freqs()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_clocks.c48 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
63 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_get_engine_clock()
64 if (post_div == 2) in radeon_legacy_get_engine_clock()
66 else if (post_div == 3) in radeon_legacy_get_engine_clock()
68 else if (post_div == 4) in radeon_legacy_get_engine_clock()
78 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
93 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock()
94 if (post_div == 2) in radeon_legacy_get_memory_clock()
96 else if (post_div == 3) in radeon_legacy_get_memory_clock()
98 else if (post_div == 4) in radeon_legacy_get_memory_clock()
[all …]
H A Dradeon_display.c922 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, in avivo_get_fb_ref_div() argument
927 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); in avivo_get_fb_ref_div()
930 *ref_div = min(max(den/post_div, 1u), ref_div_max); in avivo_get_fb_ref_div()
931 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in avivo_get_fb_ref_div()
965 unsigned post_div_min, post_div_max, post_div; in radeon_compute_pll_avivo() local
996 post_div_min = pll->post_div; in radeon_compute_pll_avivo()
997 post_div_max = pll->post_div; in radeon_compute_pll_avivo()
1041 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { in radeon_compute_pll_avivo()
1043 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, in radeon_compute_pll_avivo()
1046 (ref_div * post_div)); in radeon_compute_pll_avivo()
[all …]
H A Dradeon_legacy_tv.c861 int post_div; in get_post_div() local
863 case 1: post_div = 0; break; in get_post_div()
864 case 2: post_div = 1; break; in get_post_div()
865 case 3: post_div = 4; break; in get_post_div()
866 case 4: post_div = 2; break; in get_post_div()
867 case 6: post_div = 6; break; in get_post_div()
868 case 8: post_div = 3; break; in get_post_div()
869 case 12: post_div = 7; break; in get_post_div()
871 default: post_div = 5; break; in get_post_div()
873 return post_div; in get_post_div()
H A Dradeon_rv730_dpm.c69 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
70 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
85 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
86 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
147 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()
148 (dividers.post_div & 0xf) + 2; in rv730_populate_mclk_value()
160 mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_mclk_value()
161 mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_mclk_value()
H A Dradeon_rv740_dpm.c148 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
154 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
165 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
222 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value()
239 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value()
252 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
H A Dradeon_uvd.c929 unsigned post_div = vco_freq / target_freq; in radeon_uvd_calc_upll_post_div() local
932 if (post_div < pd_min) in radeon_uvd_calc_upll_post_div()
933 post_div = pd_min; in radeon_uvd_calc_upll_post_div()
936 if ((vco_freq / post_div) > target_freq) in radeon_uvd_calc_upll_post_div()
937 post_div += 1; in radeon_uvd_calc_upll_post_div()
940 if (post_div > pd_even && post_div % 2) in radeon_uvd_calc_upll_post_div()
941 post_div += 1; in radeon_uvd_calc_upll_post_div()
943 return post_div; in radeon_uvd_calc_upll_post_div()
H A Dradeon_legacy_crtc.c772 } *post_div, post_divs[] = { in radeon_set_pll() local
838 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_set_pll()
839 if (post_div->divider == post_divider) in radeon_set_pll()
843 if (!post_div->divider) in radeon_set_pll()
844 post_div = &post_divs[0]; in radeon_set_pll()
859 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); in radeon_set_pll()
H A Dradeon_rs780_dpm.c94 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
460 (min_dividers.post_div != max_dividers.post_div) || in rs780_set_engine_clock_scaling()
462 (max_dividers.post_div != current_max_dividers.post_div)) in rs780_set_engine_clock_scaling()
996 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_debugfs_print_current_performance_level() local
999 (post_div * ref_div); in rs780_dpm_debugfs_print_current_performance_level()
1019 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_get_current_sclk() local
1022 (post_div * ref_div); in rs780_dpm_get_current_sclk()
H A Dradeon_atombios_crtc.c837 u32 post_div, in atombios_crtc_program_pll() argument
864 args.v1.ucPostDiv = post_div; in atombios_crtc_program_pll()
874 args.v2.ucPostDiv = post_div; in atombios_crtc_program_pll()
884 args.v3.ucPostDiv = post_div; in atombios_crtc_program_pll()
901 args.v5.ucPostDiv = post_div; in atombios_crtc_program_pll()
930 args.v6.ucPostDiv = post_div; in atombios_crtc_program_pll()
1077 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in atombios_crtc_set_pll() local
1104 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()
1109 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1112 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
[all …]
H A Dradeon_mode.h173 uint32_t post_div; member
581 u32 post_div; member
621 u32 post_div; member
H A Dradeon_rv770_dpm.c337 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
426 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
456 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
518 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; in rv770_populate_sclk_value()
532 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv770_populate_sclk_value()
533 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv770_populate_sclk_value()
H A Dradeon_kv_dpm.c551 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
854 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
860 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
922 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
985 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
1044 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
H A Dnouveau_nvkm_subdev_clk_mcp77.c60 u32 post_div = 0; in read_pll() local
66 post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); in read_pll()
69 post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; in read_pll()
79 clock = clock / post_div; in read_pll()
/netbsd-src/sys/arch/arm/sunxi/
H A Dsun9i_a80_cpusclk.c178 const u_int post_div = __SHIFTOUT(val, CPUS_POST_DIV); in sun9i_a80_cpusclk_get_rate() local
183 rate /= (post_div + 1); in sun9i_a80_cpusclk_get_rate()
/netbsd-src/sys/arch/arm/nxp/
H A Dimx_ccm_composite.c86 const u_int post_div = __SHIFTOUT(val, TARGET_ROOT_POST_PODF) + 1; in imx_ccm_composite_get_rate() local
88 return prate / pre_div / post_div; in imx_ccm_composite_get_rate()
/netbsd-src/sys/arch/arm/broadcom/
H A Dbcm53xx_board.c325 u_int post_div = __SHIFTOUT(pll_dividers, PLL_DIVIDERS_POST_DIV); in bcm53xx_get_ddr_freq() local
332 clk->clk_ddr = (clk->clk_ddr_ref / pdiv) * ndiv / (2 + post_div); in bcm53xx_get_ddr_freq()
/netbsd-src/sys/dev/pci/
H A Dmachfb.c937 int post_div, dot_clock, vrefresh, vrefresh2; in mach64_get_mode() local
971 post_div = 8; in mach64_get_mode()
974 post_div = 4; in mach64_get_mode()
977 post_div = 2; in mach64_get_mode()
980 post_div = 1; in mach64_get_mode()
983 dot_clock = (2 * ref_freq * vclk_fb_div) / (ref_div * post_div); in mach64_get_mode()

12