| /netbsd-src/sys/arch/evbarm/stand/board/ |
| H A D | sscom.c | 206 int mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT; in get_com_freq() local
211 clk = (XTAL_CLK * 1000000 * (8 + mdiv)) / ((pdiv + 2) << sdiv); in get_com_freq()
213 clk = (XTAL_CLK * (8 + mdiv)) / ((pdiv + 2) << sdiv); in get_com_freq()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| H A D | nouveau_nvkm_subdev_clk_gk104.c | 40 u32 mdiv; member
325 info->mdiv |= 0x80000000; in calc_clk()
326 info->mdiv |= div1D; in calc_clk()
332 info->mdiv |= 0x80000000; in calc_clk()
333 info->mdiv |= div1P << 8; in calc_clk()
421 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv); in gk104_clk_prog_3()
423 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv); in gk104_clk_prog_3()
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| H A D | nouveau_nvkm_subdev_clk_gf100.c | 40 u32 mdiv; member
312 info->mdiv |= 0x80000000; in calc_clk()
313 info->mdiv |= div1D; in calc_clk()
319 info->mdiv |= 0x80000000; in calc_clk()
320 info->mdiv |= div1P << 8; in calc_clk()
417 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f3f, info->mdiv); in gf100_clk_prog_4()
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| H A D | nouveau_nvkm_subdev_clk_base.c | 405 lo /= clock->mdiv; in nvkm_pstate_info()
406 hi /= clock->mdiv; in nvkm_pstate_info()
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| /netbsd-src/sys/arch/arm/s3c2xx0/ |
| H A D | s3c2800.c | 208 int mdiv, pdiv, sdiv; in s3c2800_clock_freq2() local
214 mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT; in s3c2800_clock_freq2()
218 f = ((mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv)); in s3c2800_clock_freq2()
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| H A D | s3c2410.c | 209 int mdiv, pdiv, sdiv; in s3c24x0_clock_freq2() local
215 mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT; in s3c24x0_clock_freq2()
219 f = ((mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv)); in s3c24x0_clock_freq2()
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| H A D | s3c2440.c | 241 int mdiv, pdiv, sdiv; in s3c24x0_clock_freq2() local
248 mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT; in s3c24x0_clock_freq2()
252 f = ((mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv)) * 2; in s3c24x0_clock_freq2()
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| /netbsd-src/sys/arch/evbarm/smdk2xx0/ |
| H A D | smdk2410_start.S | 178 .macro clock_data hdivn, pdivn, mdiv, pdiv, sdiv
180 .word (\mdiv)<<PLLCON_MDIV_SHIFT | (\pdiv)<<PLLCON_PDIV_SHIFT | (\sdiv)<<PLLCON_SDIV_SHIFT
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| /netbsd-src/sys/arch/evbarm/stand/boot2440/ |
| H A D | main.c | 411 int mdiv, pdiv, sdiv; in s3c24x0_clock_freq2() local
418 mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT; in s3c24x0_clock_freq2()
422 f = ((mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv)) * 2; in s3c24x0_clock_freq2()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/ |
| H A D | nouveau_nvkm_engine_device_ctrl.c | 131 args->v0.min = lo / domain->mdiv; in nvkm_control_mthd_pstate_attr()
132 args->v0.max = hi / domain->mdiv; in nvkm_control_mthd_pstate_attr()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/ |
| H A D | clk.h | 82 int mdiv; member
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/mcore/ |
| H A D | mcore.opt | 41 mdiv
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/mcore/ |
| H A D | mcore.opt | 41 mdiv
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/riscv/ |
| H A D | riscv.opt | 69 mdiv
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| /netbsd-src/sys/arch/macppc/dev/ |
| H A D | snapper.c | 1713 int clksrc, mdiv, sdiv; in snapper_set_rate() local
1739 mdiv = clksrc / MCLK; /* 4 */ in snapper_set_rate()
1742 switch (mdiv) { in snapper_set_rate()
1753 reg |= ((mdiv / 2 - 1) << 24) & 0x1f000000; in snapper_set_rate()
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/csky/ |
| H A D | csky.opt | 128 mdiv
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/csky/ |
| H A D | csky.opt | 149 mdiv
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/m68k/ |
| H A D | m68k.opt | 129 mdiv
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/m68k/ |
| H A D | m68k.opt | 129 mdiv
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/riscv/ |
| H A D | riscv.opt | 77 mdiv
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/sh/ |
| H A D | sh.opt | 209 mdiv=
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/sh/ |
| H A D | sh.opt | 209 mdiv=
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| /netbsd-src/sys/arch/evbarm/conf/ |
| H A D | SMDK2410 | 37 # hdivn, pdivn, mdiv, pdiv, sdiv
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| H A D | intel_display.c | 8221 u32 mdiv; in vlv_prepare_pll() local
8260 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); in vlv_prepare_pll()
8261 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); in vlv_prepare_pll()
8262 mdiv |= ((bestn << DPIO_N_SHIFT)); in vlv_prepare_pll()
8263 mdiv |= (1 << DPIO_K_SHIFT); in vlv_prepare_pll()
8270 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); in vlv_prepare_pll()
8271 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
8273 mdiv |= DPIO_ENABLE_CALIBRATION; in vlv_prepare_pll()
8274 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
9063 u32 mdiv; in vlv_crtc_clock_get() local
[all …]
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/arc/ |
| H A D | arc.opt | 130 mdiv-rem
|