| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | CallingConvLower.cpp | 76 if (ValAssign.isRegLoc()) { in IsShadowAllocatedReg()
228 HaveRegParm = Locs.back().isRegLoc(); in getRemainingRegParmsForType()
234 if (Locs[I].isRegLoc()) in getRemainingRegParmsForType()
288 Loc1.isRegLoc() != Loc2.isRegLoc() || in resultsCompatible()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 113 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
154 assert(VA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
155 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
284 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
325 assert(VA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
326 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
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| H A D | ARMFastISel.cpp | 1895 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1901 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
1975 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1987 assert(VA.isRegLoc() && NextVA.isRegLoc() && in ProcessCallArgs()
2117 if (!VA.isRegLoc()) in SelectRet()
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| H A D | ARMISelLowering.cpp | 2208 if (NextVA.isRegLoc()) in PassF64ArgInRegs()
2375 if (VA.isRegLoc()) { in LowerCall()
2387 } else if (VA.isRegLoc()) { in LowerCall()
2881 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
2883 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
2886 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
2888 if (!ArgLocs[++i].isRegLoc()) in IsEligibleForTailCallOptimization()
2891 } else if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
2991 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
4317 if (VA.isRegLoc()) { in LowerFormalArguments()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 284 if (VA.isRegLoc()) { in LowerCall()
377 if (VA.isRegLoc()) { in lowerCallResult()
482 if (VA.isRegLoc()) { in LowerCallArguments()
634 if (VA.isRegLoc()) in LowerReturn()
662 if (!VA.isRegLoc()) in LowerReturn()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | CallingConvLower.h | 145 bool isRegLoc() const { return !isMem; } in isRegLoc() function
150 Register getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 920 if (!ArgLoc.isRegLoc()) in parametersInCSRMatch()
999 if (Loc1.isRegLoc() != Loc2.isRegLoc()) in resultsCompatible()
1002 if (Loc1.isRegLoc()) { in resultsCompatible()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 320 if (VA.isRegLoc()) { in LowerFormalArguments()
441 if (VA.isRegLoc()) in LowerCall()
528 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 233 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
316 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
414 if (VA.isRegLoc()) { in LowerFormalArguments_32()
593 if (VA.isRegLoc()) { in LowerFormalArguments_64()
866 if (VA.isRegLoc()) { in LowerCall_32()
870 if (NextVA.isRegLoc()) { in LowerCall_32()
900 if (VA.isRegLoc()) { in LowerCall_32()
1052 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1164 if (VA.isRegLoc()) { in LowerCall_64()
1199 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && in LowerCall_64()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 626 if (VA.isRegLoc()) { in LowerCall()
671 if (VA.isRegLoc()) in LowerCall()
892 if (VA.isRegLoc()) { in LowerFormalArguments()
1032 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
1207 if (!ArgLocs[i].isRegLoc()) in IsEligibleForTailCallOptimization()
1250 if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
1274 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1068 if (VA.isRegLoc()) { in LowerCallResult()
1162 if (VA.isRegLoc()) { in LowerCCCCallTo()
1299 if (VA.isRegLoc()) { in LowerCCCArguments()
1470 if (VA.isRegLoc()) in LowerReturn()
1498 if (!VA.isRegLoc()) in LowerReturn()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 458 if (VA.isRegLoc()) { in LowerCCCArguments()
555 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
685 if (VA.isRegLoc()) { in LowerCCCCallTo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 640 if (VA.isRegLoc()) { in LowerCCCArguments()
762 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
848 if (VA.isRegLoc()) { in LowerCCCCallTo()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 1397 !VA.isRegLoc() || VA.needsCustom()) in processCallArgs()
1505 assert(VA.isRegLoc() && "Can only return in registers!"); in finishCall()
1745 assert(VA.isRegLoc() && "Can only return in registers!"); in SelectRet()
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| H A D | PPCISelLowering.cpp | 4002 if (VA.isRegLoc()) { in LowerFormalArguments_32SVR4()
5092 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
5807 if (VA.isRegLoc()) { in LowerCall_32SVR4()
6922 assert(I != End && ArgLocs[I].isRegLoc() && ArgLocs[I].needsCustom() && in LowerFormalArguments_AIX()
6942 if (I != End && ArgLocs[I].isRegLoc() && ArgLocs[I].needsCustom()) { in LowerFormalArguments_AIX()
6952 if (VA.isRegLoc()) { in LowerFormalArguments_AIX()
6975 assert(VA.isRegLoc() && "MemLocs should already be handled."); in LowerFormalArguments_AIX()
7017 for (; Offset != StackSize && ArgLocs[I].isRegLoc(); in LowerFormalArguments_AIX()
7039 if (VA.isRegLoc() && !VA.needsCustom()) { in LowerFormalArguments_AIX()
7198 while (LoadOffset + PtrByteSize <= ByValSize && ArgLocs[I].isRegLoc()) { in LowerCall_AIX()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 29 if (VA.isRegLoc()) { in assign()
|
| H A D | MipsFastISel.cpp | 1229 if (VA.isRegLoc() && !VA.needsCustom()) { in processCallArgs()
1720 if (!VA.isRegLoc()) in selectRet()
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| H A D | MipsISelLowering.cpp | 3282 if (VA.isRegLoc()) { in LowerCall()
3335 if (VA.isRegLoc()) { in LowerCall()
3496 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
3645 bool IsRegLoc = VA.isRegLoc(); in LowerFormalArguments()
3813 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 339 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
416 if (VA.isRegLoc()) { in LowerFormalArguments()
674 if (VA.isRegLoc()) { in LowerCall()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 733 if (ArgLoc.isRegLoc()) in areCalleeOutgoingArgsTailCallable()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1148 if (VA.isRegLoc()) { in LowerFormalArguments()
1465 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 518 if (VA.isRegLoc()) in LowerCall()
834 if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8) in LowerFormalArguments()
837 bool InReg = VA.isRegLoc() && in LowerFormalArguments()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 7072 assert(VA.isRegLoc() && "Expected register VA assignment"); in unpackF64OnRV32DSoftABI()
7265 else if (VA.isRegLoc()) in LowerFormalArguments()
7519 if (IsF64OnRV32DSoftABI && VA.isRegLoc()) { in LowerCall()
7600 if (VA.isRegLoc()) { in LowerCall()
7788 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
7792 assert(VA.isRegLoc() && "Expected return via registers"); in LowerReturn()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1235 if (!VA.isRegLoc()) in X86SelectRet()
3387 if (VA.isRegLoc()) { in fastLowerCall()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1399 if (VA.isRegLoc()) { in LowerFormalArguments()
1527 if (!VA.isRegLoc()) in canUseSiblingCall()
1624 if (VA.isRegLoc()) in LowerCall()
1785 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
|