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Searched refs:getLocReg (Results 1 – 25 of 30) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp114 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
165 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
166 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
285 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
331 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
332 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
H A DARMFastISel.cpp1977 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); in ProcessCallArgs()
1978 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1991 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
1992 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
1994 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1995 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2041 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2042 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2044 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2045 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
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H A DARMISelLowering.cpp2121 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
2126 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
2140 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
2144 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
2154 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
2206 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id))); in PassF64ArgInRegs()
2209 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id))); in PassF64ArgInRegs()
2398 CSInfo.emplace_back(VA.getLocReg(), i); in LowerCall()
2399 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
3054 DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp249 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
253 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
256 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn_32()
260 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
343 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
351 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
355 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
419 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
432 Register loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp285 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
380 DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), Glue); in lowerCallResult()
493 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCallArguments()
665 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
670 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp334 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
442 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
530 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
535 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
568 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), in LowerCallResult()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DCallingConvLower.cpp77 for (MCRegAliasIterator AI(ValAssign.getLocReg(), &TRI, true); in IsShadowAllocatedReg()
235 Regs.push_back(MCPhysReg(Locs[I].getLocReg())); in getRemainingRegParmsForType()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp747 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); in handleAssignments()
923 MCRegister PhysReg = ArgLoc.getLocReg(); in parametersInCSRMatch()
1004 if (Loc1.getLocReg() != Loc2.getLocReg()) in resultsCompatible()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp140 Register PhysReg = VA.getLocReg(); in assignValueToReg()
242 Register PhysReg = VA.getLocReg(); in assignValueToReg()
373 VA.getLocReg(), VA.getLocVT(), LocInfo); in setLocInfo()
H A DMipsFastISel.cpp1231 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
1232 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
1302 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1303 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
1728 Register DestReg = VA.getLocReg(); in selectRet()
1769 RetRegs.push_back(VA.getLocReg()); in selectRet()
H A DMipsISelLowering.cpp3294 Register LocRegLo = VA.getLocReg(); in LowerCall()
3336 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
3340 if (Mips::AFGR64RegClass.contains(VA.getLocReg())) in LowerCall()
3346 CSInfo.emplace_back(VA.getLocReg(), i); in LowerCall()
3498 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
3665 Register ArgReg = VA.getLocReg(); in LowerFormalArguments()
3852 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); in LowerReturn()
3856 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp464 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
557 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
561 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
686 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
787 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(), in LowerCallResult()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp654 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
764 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
770 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
849 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
947 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1159 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
1313 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1411 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(), in LowerCallResult()
1467 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
1471 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h150 Register getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg() function
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FastISel.cpp1240 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in X86SelectRet()
1270 Register DstReg = VA.getLocReg(); in X86SelectRet()
1279 RetRegs.push_back(VA.getLocReg()); in X86SelectRet()
3389 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in fastLowerCall()
3390 OutRegs.push_back(VA.getLocReg()); in fastLowerCall()
3539 Register SrcReg = VA.getLocReg(); in fastLowerCall()
3558 InRegs.push_back(VA.getLocReg()); in fastLowerCall()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1069 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), in LowerCallResult()
1163 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
1313 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1501 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
1506 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp627 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
849 Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), CopyVT, InFlag) in LowerCallResult()
900 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
1049 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), ValToCopy, Flag); in LowerReturn()
1051 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
1276 unsigned Reg = VA.getLocReg(); in IsEligibleForTailCallOptimization()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEISelLowering.cpp376 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn()
380 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
422 MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT())); in LowerFormalArguments()
675 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
756 unsigned Reg = VA.getLocReg(); in LowerCall()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp244 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Val, Flag); in LowerReturn()
248 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
372 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
386 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
519 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
866 MRI.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
867 HFL.FirstVarArgSavedReg = NextSingleReg(*RC, VA.getLocReg()); in LowerFormalArguments()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4049 unsigned RegLo = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
4050 unsigned RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC); in LowerFormalArguments_32SVR4()
4058 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
5097 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
5102 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
5111 VA.getLocReg(), VA.getLocVT(), InFlag); in LowerCallResult()
5814 RegsToPass.push_back(std::make_pair(VA.getLocReg(), SVal.getValue(0))); in LowerCall_32SVR4()
5817 RegsToPass.push_back(std::make_pair(ArgLocs[++i].getLocReg(), in LowerCall_32SVR4()
5820 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32SVR4()
6930 MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64)); in LowerFormalArguments_AIX()
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H A DPPCFastISel.cpp1515 unsigned SourcePhysReg = VA.getLocReg(); in finishCall()
1722 Register RetReg = VA.getLocReg(); in SelectRet()
1746 RetRegs.push_back(VA.getLocReg()); in SelectRet()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp6993 RegInfo.addLiveIn(VA.getLocReg(), VReg); in unpackFromRegLoc()
7075 RegInfo.addLiveIn(VA.getLocReg(), LoVReg); in unpackF64OnRV32DSoftABI()
7078 if (VA.getLocReg() == RISCV::X17) { in unpackF64OnRV32DSoftABI()
7087 RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg); in unpackF64OnRV32DSoftABI()
7525 Register RegLo = VA.getLocReg(); in LowerCall()
7602 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
7714 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
7720 assert(VA.getLocReg() == ArgGPRs[0] && "Unexpected reg assignment"); in LowerCall()
7797 Register RegLo = VA.getLocReg(); in LowerReturn()
7816 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); in LowerReturn()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3045 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
3046 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
3110 .addReg(RVLocs[0].getLocReg()); in finishCall()
3111 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
3802 Register DestReg = VA.getLocReg(); in selectRet()
3845 RetRegs.push_back(VA.getLocReg()); in selectRet()
H A DAArch64ISelLowering.cpp4908 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
5225 SDValue Val = CopiedRegs.lookup(VA.getLocReg()); in LowerCallResult()
5228 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag); in LowerCallResult()
5231 CopiedRegs[VA.getLocReg()] = Val; in LowerCallResult()
5741 if (RegsUsed.count(VA.getLocReg())) { in LowerCall()
5749 return Elt.first == VA.getLocReg(); in LowerCall()
5757 return ArgReg.Reg == VA.getLocReg(); in LowerCall()
5760 RegsToPass.emplace_back(VA.getLocReg(), Arg); in LowerCall()
5761 RegsUsed.insert(VA.getLocReg()); in LowerCall()
5764 CSInfo.emplace_back(VA.getLocReg(), i); in LowerCall()
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