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/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/therm/
H A Dnouveau_nvkm_subdev_therm_fanpwm.c49 u32 divs, duty; in nvkm_fanpwm_get() local
52 ret = therm->func->pwm_get(therm, fan->func.line, &divs, &duty); in nvkm_fanpwm_get()
53 if (ret == 0 && divs) { in nvkm_fanpwm_get()
54 divs = max(divs, duty); in nvkm_fanpwm_get()
56 duty = divs - duty; in nvkm_fanpwm_get()
57 return (duty * 100) / divs; in nvkm_fanpwm_get()
68 u32 divs, duty; in nvkm_fanpwm_set() local
71 divs = fan->base.perf.pwm_divisor; in nvkm_fanpwm_set()
73 divs = 1; in nvkm_fanpwm_set()
75 divs = therm->func->pwm_clock(therm, fan->func.line); in nvkm_fanpwm_set()
[all …]
H A Dnouveau_nvkm_subdev_therm_gf119.c72 gf119_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in gf119_fan_pwm_get() argument
80 *divs = nvkm_rd32(device, 0x00e114 + (indx * 8)); in gf119_fan_pwm_get()
85 *divs = nvkm_rd32(device, 0x0200d8) & 0x1fff; in gf119_fan_pwm_get()
94 gf119_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in gf119_fan_pwm_set() argument
101 nvkm_wr32(device, 0x00e114 + (indx * 8), divs); in gf119_fan_pwm_set()
104 nvkm_mask(device, 0x0200d8, 0x1fff, divs); /* keep the high bits */ in gf119_fan_pwm_set()
H A Dnouveau_nvkm_subdev_therm_nv40.c126 nv40_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in nv40_fan_pwm_get() argument
134 *divs = (reg & 0x00007fff); in nv40_fan_pwm_get()
141 *divs = nvkm_rd32(device, 0x0015f8); in nv40_fan_pwm_get()
154 nv40_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in nv40_fan_pwm_set() argument
159 nvkm_mask(device, 0x0010f0, 0x7fff7fff, (duty << 16) | divs); in nv40_fan_pwm_set()
162 nvkm_wr32(device, 0x0015f8, divs); in nv40_fan_pwm_set()
H A Dnouveau_nvkm_subdev_therm_gm107.c39 gm107_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in gm107_fan_pwm_get() argument
42 *divs = nvkm_rd32(device, 0x10eb20) & 0x1fff; in gm107_fan_pwm_get()
48 gm107_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in gm107_fan_pwm_set() argument
51 nvkm_mask(device, 0x10eb10, 0x1fff, divs); /* keep the high bits */ in gm107_fan_pwm_set()
H A Dnouveau_nvkm_subdev_therm_nv50.c71 nv50_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in nv50_fan_pwm_get() argument
79 *divs = nvkm_rd32(device, 0x00e114 + (id * 8)); in nv50_fan_pwm_get()
88 nv50_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in nv50_fan_pwm_set() argument
95 nvkm_wr32(device, 0x00e114 + (id * 8), divs); in nv50_fan_pwm_set()
/netbsd-src/sys/arch/arm/rockchip/
H A Drk_cru_arm.c57 const uint32_t val = CRU_READ(sc, arm->divs[0].reg); in rk_cru_arm_get_rate()
58 const u_int div = __SHIFTOUT(val, arm->divs[0].mask) + 1; in rk_cru_arm_get_rate()
102 for (int i = 0; i < __arraycount(arm->divs); i++) { in rk_cru_arm_set_rate_rates()
103 if (arm->divs[i].reg == 0 && arm->divs[i].mask == 0) in rk_cru_arm_set_rate_rates()
106 const uint32_t write_mask = arm->divs[i].mask << 16; in rk_cru_arm_set_rate_rates()
108 arm->divs[i].mask); in rk_cru_arm_set_rate_rates()
109 CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val); in rk_cru_arm_set_rate_rates()
157 for (int i = 0; i < __arraycount(cpu_rate->divs); i++) { in rk_cru_arm_set_rate_cpurates()
158 if (cpu_rate->divs[i].reg == 0 && cpu_rate->divs[i].mask == 0 && in rk_cru_arm_set_rate_cpurates()
159 cpu_rate->divs[i].val == 0) in rk_cru_arm_set_rate_cpurates()
[all …]
H A Drk_cru.h161 struct rk_regmaskval divs[4]; member
176 struct rk_regmask divs[4]; member
202 .u.arm.divs[0].reg = (_reg), \
203 .u.arm.divs[0].mask = (_div_mask), \
236 .u.arm.divs[0].reg = (_div_reg), \
237 .u.arm.divs[0].mask = (_div_mask), \
248 .u.arm.divs[0].reg = (_div0_reg), \
249 .u.arm.divs[0].mask = (_div0_mask), \
250 .u.arm.divs[1].reg = (_div1_reg), \
251 .u.arm.divs[1].mask = (_div1_mask), \
[all …]
H A Drk3399_cru.c149 .divs[0] = { .reg = (_reg0), .mask = (_reg0_mask), .val = (_reg0_val) },\
150 .divs[1] = { .reg = (_reg1), .mask = (_reg1_mask), .val = (_reg1_val) },\
H A Drk3588_cru.c131 .divs = { \
195 .divs[0] = { \
204 .divs[1] = { \
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/h8300/
H A Ddiv.s19 ;; divs.w rs, rd
23 divs.w r2, r1
43 ;; divs.w xx:4, rd
46 divs.w #2:4, r1
66 ;; divs.l ers, erd
70 divs.l er2, er1
90 ;; divs.l xx:4, rd
93 divs.l #2:4, er1
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/sh/
H A Ddiv.s1 # sh testcase for divs and divu
13 divs r0, r1
33 divs r0, r1
53 divs r0, r1
73 divs r0, r1
96 divs r0, r1
/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
H A Dnouveau_nvkm_subdev_clk_mcp77.c217 int divs = 0; in mcp77_clk_calc() local
221 out = calc_P(nvkm_clk_read(&clk->base, nv_clk_src_hclkm4), core, &divs); in mcp77_clk_calc()
228 clk->cctrl = divs << 16; in mcp77_clk_calc()
252 out = calc_P((core << 1), shader, &divs); in mcp77_clk_calc()
256 (divs + P2) <= 7) { in mcp77_clk_calc()
258 clk->sctrl = (divs + P2) << 16; in mcp77_clk_calc()
267 out = calc_P(core, vdec, &divs); in mcp77_clk_calc()
271 clk->vdiv = divs << 16; in mcp77_clk_calc()
H A Dnouveau_nvkm_subdev_clk_nv50.c452 clk_mask(hwsq, divs, divsm, divsv); in nv50_clk_calc()
/netbsd-src/external/gpl3/gdb/dist/gdb/testsuite/gdb.disasm/
H A Dt06_ari2.s180 divs.w #0xf:4,r1 ;01d651f1
182 divs.w r3,r1 ;01d25131
184 divs.l #0xf:4,er1 ;01d653f1
186 divs.l er3,er1 ;01d25331
/netbsd-src/external/mit/isl/dist/test_inputs/codegen/
H A Dunroll7.in2 # Older versions of isl would abort on unknown divs.
/netbsd-src/external/gpl3/gcc/dist/gcc/config/h8300/
H A Ddivmod.md40 { return <MODE>mode == HImode ? "divs.w\\t%T2,%T0" : "divs.l\\t%S2,%S0"; }
/netbsd-src/sys/arch/sgimips/dev/
H A Dscn.c358 } divs[] = { variable
365 #define DIVS (sizeof(divs)/sizeof(divs[0]))
496 for (i = 0; i < DIVS && divs[i].speed <= dp->counter; i++) { in scn_setchip()
497 if (divs[i].speed == dp->counter) { in scn_setchip()
498 div = divs[i].div; in scn_setchip()
/netbsd-src/sys/dev/
H A Dsequencer.c1193 seq_timer_waitabs(struct sequencer_softc *sc, uint32_t divs) in seq_timer_waitabs() argument
1203 t->divs_lastevent = divs; in seq_timer_waitabs()
1204 divs -= t->divs_lastchange; in seq_timer_waitabs()
1205 usec = (long long)divs * (long long)t->usperdiv; /* convert to usec */ in seq_timer_waitabs()
1209 divs, when.tv_sec, (uint64_t)when.tv_usec)); in seq_timer_waitabs()
/netbsd-src/sys/arch/m68k/060sp/dist/
H A Dilsp.s115 # divs.l #
205 tst.b POSNEG(%a6) # do divs, divu separately
208 # it was a divs.l, so ccode setting is a little more complicated...
H A Ditest.s1144 divs.l %d1,%d2:%d3
1166 divs.l %d1,%d2:%d3
1190 divs.l %d1,%d2:%d3
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/
H A Ddivq.s25 divs (r0, r1);
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/m68k/
H A Dm68k.md101 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
3534 return "divs%.l %2,%0";
3538 return "rems%.l %2,%3:%0\;divs%.l %2,%0";
3552 return "divs%.l %2,%0";
3608 "ext%.l %0\;divs%.w %2,%0" :
3609 "extl %0\;divs %2,%0",
/netbsd-src/external/gpl3/gcc/dist/gcc/config/m68k/
H A Dm68k.md101 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
3534 return "divs%.l %2,%0";
3538 return "rems%.l %2,%3:%0\;divs%.l %2,%0";
3552 return "divs%.l %2,%0";
3608 "ext%.l %0\;divs%.w %2,%0" :
3609 "extl %0\;divs %2,%0",
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DREADME-SSE.txt822 and emit 3 mulsd in place of the divs. This can be done as a target-independent
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEInstrInfo.td1209 defm DIVSWSX : RRNCm<"divs.w.sx", 0x7B, I32, i32, sdiv>;
1210 let cx = 1 in defm DIVSWZX : RRNCm<"divs.w.zx", 0x7B, I32, i32>;
1213 defm DIVSL : RRNCm<"divs.l", 0x7F, I64, i64, sdiv>;

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