Home
last modified time | relevance | path

Searched refs:dev_priv (Results 1 – 25 of 278) sorted by relevance

12345678910>>...12

/netbsd-src/sys/external/bsd/drm2/dist/drm/vmwgfx/
H A Dvmwgfx_drv.c363 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) in vmw_dummy_query_bo_create() argument
380 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, in vmw_dummy_query_bo_create()
405 dev_priv->dummy_query_bo = vbo; in vmw_dummy_query_bo_create()
420 static int vmw_request_device_late(struct vmw_private *dev_priv) in vmw_request_device_late() argument
424 if (dev_priv->has_mob) { in vmw_request_device_late()
425 ret = vmw_otables_setup(dev_priv); in vmw_request_device_late()
433 if (dev_priv->cman) { in vmw_request_device_late()
434 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, in vmw_request_device_late()
437 struct vmw_cmdbuf_man *man = dev_priv->cman; in vmw_request_device_late()
439 dev_priv->cman = NULL; in vmw_request_device_late()
[all …]
H A Dvmwgfx_irq.c60 struct vmw_private *dev_priv = vmw_priv(dev); in vmw_thread_fn() local
64 atomic_store_relaxed(&dev_priv->irqthread_scheduled, false); in vmw_thread_fn()
68 dev_priv->irqthread_pending)) { in vmw_thread_fn()
69 spin_lock(&dev_priv->fence_lock); in vmw_thread_fn()
70 vmw_fences_update(dev_priv->fman); in vmw_thread_fn()
71 DRM_SPIN_WAKEUP_ALL(&dev_priv->fence_queue, in vmw_thread_fn()
72 &dev_priv->fence_lock); in vmw_thread_fn()
73 spin_unlock(&dev_priv->fence_lock); in vmw_thread_fn()
78 dev_priv->irqthread_pending)) { in vmw_thread_fn()
79 vmw_cmdbuf_irqthread(dev_priv->cman); in vmw_thread_fn()
[all …]
H A Dvmwgfx_fifo.c46 bool vmw_fifo_have_3d(struct vmw_private *dev_priv) in vmw_fifo_have_3d() argument
48 u32 *fifo_mem = dev_priv->mmio_virt; in vmw_fifo_have_3d()
50 const struct vmw_fifo_state *fifo = &dev_priv->fifo; in vmw_fifo_have_3d()
52 if (!(dev_priv->capabilities & SVGA_CAP_3D)) in vmw_fifo_have_3d()
55 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { in vmw_fifo_have_3d()
58 if (!dev_priv->has_mob) in vmw_fifo_have_3d()
61 spin_lock(&dev_priv->cap_lock); in vmw_fifo_have_3d()
62 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D); in vmw_fifo_have_3d()
63 result = vmw_read(dev_priv, SVGA_REG_DEV_CAP); in vmw_fifo_have_3d()
64 spin_unlock(&dev_priv->cap_lock); in vmw_fifo_have_3d()
[all …]
/netbsd-src/sys/external/bsd/drm/dist/shared-core/
H A Dradeon_cp.c45 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
47 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr) in RADEON_READ_MM() argument
52 ret = DRM_READ32( dev_priv->mmio, addr ); in RADEON_READ_MM()
54 DRM_WRITE32( dev_priv->mmio, RADEON_MM_INDEX, addr ); in RADEON_READ_MM()
55 ret = DRM_READ32( dev_priv->mmio, RADEON_MM_DATA ); in RADEON_READ_MM()
61 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in R500_READ_MCIND() argument
70 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in RS480_READ_MCIND() argument
79 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in RS690_READ_MCIND() argument
88 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in RS600_READ_MCIND() argument
97 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in IGP_READ_MCIND() argument
[all …]
H A Dsavage_bci.c38 savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n) in savage_bci_wait_fifo_shadow() argument
40 uint32_t mask = dev_priv->status_used_mask; in savage_bci_wait_fifo_shadow()
41 uint32_t threshold = dev_priv->bci_threshold_hi; in savage_bci_wait_fifo_shadow()
46 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) in savage_bci_wait_fifo_shadow()
53 status = dev_priv->status_ptr[0]; in savage_bci_wait_fifo_shadow()
67 savage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n) in savage_bci_wait_fifo_s3d() argument
69 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s3d()
88 savage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n) in savage_bci_wait_fifo_s4() argument
90 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s4()
120 savage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e) in savage_bci_wait_event_shadow() argument
[all …]
H A Di915_suspend.c37 struct drm_i915_private *dev_priv = dev->dev_private; in i915_pipe_enabled() local
47 struct drm_i915_private *dev_priv = dev->dev_private; in i915_save_palette() local
56 array = dev_priv->save_palette_a; in i915_save_palette()
58 array = dev_priv->save_palette_b; in i915_save_palette()
66 struct drm_i915_private *dev_priv = dev->dev_private; in i915_restore_palette() local
75 array = dev_priv->save_palette_a; in i915_restore_palette()
77 array = dev_priv->save_palette_b; in i915_restore_palette()
85 struct drm_i915_private *dev_priv = dev->dev_private; in i915_read_indexed() local
93 struct drm_i915_private *dev_priv = dev->dev_private; in i915_read_ar() local
102 struct drm_i915_private *dev_priv = dev->dev_private; in i915_write_ar() local
[all …]
H A Dr600_cp.c75 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) in r600_do_wait_for_fifo() argument
79 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_fifo()
81 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_fifo()
83 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_fifo()
100 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) in r600_do_wait_for_idle() argument
104 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_idle()
106 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_idle()
107 ret = r600_do_wait_for_fifo(dev_priv, 8); in r600_do_wait_for_idle()
109 ret = r600_do_wait_for_fifo(dev_priv, 16); in r600_do_wait_for_idle()
112 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_idle()
[all …]
H A Dr128_cce.c86 drm_r128_private_t *dev_priv = dev->dev_private; in R128_READ_PLL() local
93 static void r128_status(drm_r128_private_t * dev_priv) in r128_status() argument
114 static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv) in r128_do_pixcache_flush() argument
122 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_pixcache_flush()
135 static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries) in r128_do_wait_for_fifo() argument
139 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_fifo()
152 static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv) in r128_do_wait_for_idle() argument
156 ret = r128_do_wait_for_fifo(dev_priv, 64); in r128_do_wait_for_idle()
160 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_idle()
162 r128_do_pixcache_flush(dev_priv); in r128_do_wait_for_idle()
[all …]
H A Dmga_dma.c55 int mga_do_wait_for_idle(drm_mga_private_t * dev_priv) in mga_do_wait_for_idle() argument
61 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_wait_for_idle()
77 static int mga_do_dma_reset(drm_mga_private_t * dev_priv) in mga_do_dma_reset() argument
79 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_do_dma_reset()
80 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_reset()
105 void mga_do_dma_flush(drm_mga_private_t * dev_priv) in mga_do_dma_flush() argument
107 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_flush()
115 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_dma_flush()
127 tail = primary->tail + dev_priv->primary->offset; in mga_do_dma_flush()
151 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); in mga_do_dma_flush()
[all …]
H A Di915_irq.c54 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) in i915_enable_irq() argument
57 dev_priv->irq_mask_reg, mask); in i915_enable_irq()
59 if ((dev_priv->irq_mask_reg & mask) != 0) { in i915_enable_irq()
60 dev_priv->irq_mask_reg &= ~mask; in i915_enable_irq()
61 I915_WRITE(IMR, dev_priv->irq_mask_reg); in i915_enable_irq()
67 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) in i915_disable_irq() argument
70 if ((dev_priv->irq_mask_reg & mask) != mask) { in i915_disable_irq()
71 dev_priv->irq_mask_reg |= mask; in i915_disable_irq()
72 I915_WRITE(IMR, dev_priv->irq_mask_reg); in i915_disable_irq()
88 i915_enable_pipestat(drm_i915_private_t *dev_priv, unsigned int pipe, u32 mask) in i915_enable_pipestat() argument
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/savage/
H A Dsavage_bci.c52 savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_shadow() argument
54 uint32_t mask = dev_priv->status_used_mask; in savage_bci_wait_fifo_shadow()
55 uint32_t threshold = dev_priv->bci_threshold_hi; in savage_bci_wait_fifo_shadow()
60 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) in savage_bci_wait_fifo_shadow()
67 status = dev_priv->status_ptr[0]; in savage_bci_wait_fifo_shadow()
81 savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_s3d() argument
83 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s3d()
102 savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n) in savage_bci_wait_fifo_s4() argument
104 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s4()
134 savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e) in savage_bci_wait_event_shadow() argument
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/via/
H A Dvia_dma.c72 dev_priv->dma_low += 8; \
80 dev_priv->dma_low += 8; \
83 static void via_cmdbuf_start(drm_via_private_t *dev_priv);
84 static void via_cmdbuf_pause(drm_via_private_t *dev_priv);
85 static void via_cmdbuf_reset(drm_via_private_t *dev_priv);
86 static void via_cmdbuf_rewind(drm_via_private_t *dev_priv);
87 static int via_wait_idle(drm_via_private_t *dev_priv);
88 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);
94 static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv) in via_cmdbuf_space() argument
96 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; in via_cmdbuf_space()
[all …]
H A Dvia_irq.c100 drm_via_private_t *dev_priv = dev->dev_private; in via_get_vblank_counter() local
105 return atomic_read(&dev_priv->vbl_received); in via_get_vblank_counter()
111 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; in via_driver_irq_handler() local
115 drm_via_irq_t *cur_irq = dev_priv->via_irqs; in via_driver_irq_handler()
118 status = via_read(dev_priv, VIA_REG_INTERRUPT); in via_driver_irq_handler()
120 atomic_inc(&dev_priv->vbl_received); in via_driver_irq_handler()
121 if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) { in via_driver_irq_handler()
123 if (dev_priv->last_vblank_valid) { in via_driver_irq_handler()
124 dev_priv->nsec_per_vblank = in via_driver_irq_handler()
126 dev_priv->last_vblank) >> 4; in via_driver_irq_handler()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Dintel_pch.c16 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) in intel_pch_type() argument
20 drm_dbg_kms(&dev_priv->drm, "Found Ibex Peak PCH\n"); in intel_pch_type()
21 WARN_ON(!IS_GEN(dev_priv, 5)); in intel_pch_type()
24 drm_dbg_kms(&dev_priv->drm, "Found CougarPoint PCH\n"); in intel_pch_type()
25 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
28 drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n"); in intel_pch_type()
29 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); in intel_pch_type()
33 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint PCH\n"); in intel_pch_type()
34 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
35 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); in intel_pch_type()
[all …]
H A Di915_irq.c263 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, in i915_hotplug_interrupt_update_locked() argument
269 lockdep_assert_held(&dev_priv->irq_lock); in i915_hotplug_interrupt_update_locked()
290 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, in i915_hotplug_interrupt_update() argument
294 spin_lock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
295 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); in i915_hotplug_interrupt_update()
296 spin_unlock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
305 void ilk_update_display_irq(struct drm_i915_private *dev_priv, in ilk_update_display_irq() argument
311 lockdep_assert_held(&dev_priv->irq_lock); in ilk_update_display_irq()
315 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ilk_update_display_irq()
318 new_val = dev_priv->irq_mask; in ilk_update_display_irq()
[all …]
H A Di915_drv.h197 struct drm_i915_private *dev_priv; member
270 void (*get_cdclk)(struct drm_i915_private *dev_priv,
272 void (*set_cdclk)(struct drm_i915_private *dev_priv,
275 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
311 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
312 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
537 struct drm_i915_private *dev_priv; member
1407 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) argument
1408 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) argument
1409 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) argument
[all …]
H A Di915_drv.c167 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) in i915_get_bridge_dev() argument
169 int domain = pci_domain_nr(dev_priv->drm.pdev->bus); in i915_get_bridge_dev()
171 dev_priv->bridge_dev = in i915_get_bridge_dev()
173 if (!dev_priv->bridge_dev) { in i915_get_bridge_dev()
182 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) in intel_alloc_mchbar_resource() argument
184 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_alloc_mchbar_resource()
192 if (INTEL_GEN(dev_priv) >= 4) in intel_alloc_mchbar_resource()
193 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); in intel_alloc_mchbar_resource()
194 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); in intel_alloc_mchbar_resource()
204 dev_priv->mch_res.name = "i915 MCHBAR"; in intel_alloc_mchbar_resource()
[all …]
H A Di915_suspend.c42 static void i915_save_display(struct drm_i915_private *dev_priv) in i915_save_display() argument
45 if (INTEL_GEN(dev_priv) <= 4) in i915_save_display()
46 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); in i915_save_display()
49 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_save_display()
50 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); in i915_save_display()
53 static void i915_restore_display(struct drm_i915_private *dev_priv) in i915_restore_display() argument
56 if (INTEL_GEN(dev_priv) <= 4) in i915_restore_display()
57 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); in i915_restore_display()
60 intel_fbc_global_disable(dev_priv); in i915_restore_display()
63 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) in i915_restore_display()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_psr.c83 static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, in intel_psr2_enabled() argument
90 switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in intel_psr2_enabled()
99 static void psr_irq_control(struct drm_i915_private *dev_priv) in psr_irq_control() argument
110 if (INTEL_GEN(dev_priv) >= 12) { in psr_irq_control()
112 imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder); in psr_irq_control()
114 trans_shift = dev_priv->psr.transcoder; in psr_irq_control()
119 if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ) in psr_irq_control()
167 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) in intel_psr_irq_handler() argument
169 enum transcoder cpu_transcoder = dev_priv->psr.transcoder; in intel_psr_irq_handler()
174 if (INTEL_GEN(dev_priv) >= 12) { in intel_psr_irq_handler()
[all …]
H A Dintel_cdclk.c62 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_133mhz_get_cdclk() argument
68 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_200mhz_get_cdclk() argument
74 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_266mhz_get_cdclk() argument
80 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_333mhz_get_cdclk() argument
86 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_400mhz_get_cdclk() argument
92 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_450mhz_get_cdclk() argument
98 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, in i85x_get_cdclk() argument
101 struct pci_dev *pdev = dev_priv->drm.pdev; in i85x_get_cdclk()
140 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, in i915gm_get_cdclk() argument
143 struct pci_dev *pdev = dev_priv->drm.pdev; in i915gm_get_cdclk()
[all …]
H A Dintel_fbc.c55 static inline bool fbc_supported(struct drm_i915_private *dev_priv) in fbc_supported() argument
57 return HAS_FBC(dev_priv); in fbc_supported()
87 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, in intel_fbc_calculate_cfb_size() argument
93 if (IS_GEN(dev_priv, 7)) in intel_fbc_calculate_cfb_size()
95 else if (INTEL_GEN(dev_priv) >= 8) in intel_fbc_calculate_cfb_size()
102 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) in i8xx_fbc_deactivate() argument
115 if (intel_de_wait_for_clear(dev_priv, FBC_STATUS, in i8xx_fbc_deactivate()
122 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) in i8xx_fbc_activate() argument
124 struct intel_fbc_reg_params *params = &dev_priv->fbc.params; in i8xx_fbc_activate()
135 if (IS_GEN(dev_priv, 2)) in i8xx_fbc_activate()
[all …]
H A Dintel_fifo_underrun.c61 struct drm_i915_private *dev_priv = to_i915(dev); in ivb_can_enable_err_int() local
65 lockdep_assert_held(&dev_priv->irq_lock); in ivb_can_enable_err_int()
67 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
68 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in ivb_can_enable_err_int()
79 struct drm_i915_private *dev_priv = to_i915(dev); in cpt_can_enable_serr_int() local
83 lockdep_assert_held(&dev_priv->irq_lock); in cpt_can_enable_serr_int()
85 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
86 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in cpt_can_enable_serr_int()
97 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in i9xx_check_fifo_underruns() local
101 lockdep_assert_held(&dev_priv->irq_lock); in i9xx_check_fifo_underruns()
[all …]
H A Dintel_hotplug.c94 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, in intel_hpd_pin_default() argument
109 if (IS_CNL_WITH_PORT_F(dev_priv)) in intel_hpd_pin_default()
157 static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv, in intel_hpd_irq_storm_detect() argument
160 struct i915_hotplug *hpd = &dev_priv->hotplug; in intel_hpd_irq_storm_detect()
168 (!long_hpd && !dev_priv->hotplug.hpd_short_storm_enabled)) in intel_hpd_irq_storm_detect()
190 intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv) in intel_hpd_irq_storm_switch_to_polling() argument
192 struct drm_device *dev = &dev_priv->drm; in intel_hpd_irq_storm_switch_to_polling()
200 lockdep_assert_held(&dev_priv->irq_lock); in intel_hpd_irq_storm_switch_to_polling()
214 dev_priv->hotplug.stats[pin].state != HPD_MARK_DISABLED) in intel_hpd_irq_storm_switch_to_polling()
221 dev_priv->hotplug.stats[pin].state = HPD_DISABLED; in intel_hpd_irq_storm_switch_to_polling()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/r128/
H A Dr128_cce.c62 drm_r128_private_t *dev_priv = dev->dev_private; in R128_READ_PLL() local
69 static void r128_status(drm_r128_private_t *dev_priv) in r128_status() argument
90 static int r128_do_pixcache_flush(drm_r128_private_t *dev_priv) in r128_do_pixcache_flush() argument
98 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_pixcache_flush()
110 static int r128_do_wait_for_fifo(drm_r128_private_t *dev_priv, int entries) in r128_do_wait_for_fifo() argument
114 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_fifo()
127 static int r128_do_wait_for_idle(drm_r128_private_t *dev_priv) in r128_do_wait_for_idle() argument
131 ret = r128_do_wait_for_fifo(dev_priv, 64); in r128_do_wait_for_idle()
135 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_idle()
137 r128_do_pixcache_flush(dev_priv); in r128_do_wait_for_idle()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/mga/
H A Dmga_dma.c58 int mga_do_wait_for_idle(drm_mga_private_t *dev_priv) in mga_do_wait_for_idle() argument
64 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_wait_for_idle()
80 static int mga_do_dma_reset(drm_mga_private_t *dev_priv) in mga_do_dma_reset() argument
82 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_do_dma_reset()
83 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_reset()
108 void mga_do_dma_flush(drm_mga_private_t *dev_priv) in mga_do_dma_flush() argument
110 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_flush()
118 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_dma_flush()
130 tail = primary->tail + dev_priv->primary->offset; in mga_do_dma_flush()
153 DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset)); in mga_do_dma_flush()
[all …]

12345678910>>...12