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Searched refs:bitsLE (Results 1 – 18 of 18) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DValueTypes.h273 bool bitsLE(EVT VT) const { in bitsLE() function
H A DSelectionDAG.h812 VT.getVectorElementType().bitsLE(Op.getValueType()))) &&
828 VT.getVectorElementType().bitsLE(Op.getValueType()))) &&
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp1620 assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?"); in ExpandFloatRes_LOAD()
1657 if (SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1669 if (SrcVT.bitsLE(MVT::i64)) { in ExpandFloatRes_XINT_TO_FP()
1673 } else if (SrcVT.bitsLE(MVT::i128)) { in ExpandFloatRes_XINT_TO_FP()
1689 if (isSigned || SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1980 assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?"); in ExpandFloatOp_STORE()
H A DLegalizeVectorOps.cpp1003 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()
1062 if (SrcVT.bitsLE(VT)) { in ExpandZERO_EXTEND_VECTOR_INREG()
H A DLegalizeIntegerTypes.cpp662 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); in PromoteIntRes_INT_EXTEND()
2827 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_ANY_EXTEND()
3190 if (N->getMemoryVT().bitsLE(NVT)) { in ExpandIntRes_LOAD()
3839 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_SIGN_EXTEND()
3871 if (EVT.bitsLE(Lo.getValueType())) { in ExpandIntRes_SIGN_EXTEND_INREG()
4107 if (Op.getValueType().bitsLE(NVT)) { in ExpandIntRes_ZERO_EXTEND()
4529 if (N->getMemoryVT().bitsLE(NVT)) { in ExpandIntOp_STORE()
4664 assert(PromEltVT.bitsLE(NOutVTElem) && in PromoteIntRes_EXTRACT_SUBVECTOR()
H A DSelectionDAG.cpp953 EltVT.bitsLE(Op.getValueType()))) && in VerifySDNode()
1282 if (VT.bitsLE(Op.getValueType())) in getBoolExtOrTrunc()
1299 assert(VT.bitsLE(OpVT) && "Not extending!"); in getZeroExtendInReg()
4935 assert(Operand.getValueType().bitsLE(VT) && in getNode()
4976 VT.getVectorElementType().bitsLE(Operand.getValueType()))) && in getNode()
5656 VT.bitsLE(N1.getValueType()) && in getNode()
5670 assert(EVT.bitsLE(VT.getScalarType()) && "Not extending!"); in getNode()
5685 assert(EVT.bitsLE(VT) && "Not extending!"); in getNode()
5728 assert(cast<VTSDNode>(N2)->getVT().bitsLE(VT.getScalarType()) && in getNode()
H A DTargetLowering.cpp3782 isTypeLegal(VT) && VT.bitsLE(N0.getValueType()) && in SimplifySetCC()
4082 (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) && in SimplifySetCC()
H A DDAGCombiner.cpp5351 if (ExtVT.bitsLE(Load->getMemoryVT())) in SearchForAndLoads()
11522 assert(BigA_AssertVT.bitsLE(N0.getValueType()) && in visitAssertExt()
11542 assert(BigA_AssertVT.bitsLE(N0.getValueType()) && in visitAssertExt()
19846 MinVT = (!FoundMinVT || OpSVT.bitsLE(MinVT)) ? OpSVT : MinVT; in visitCONCAT_VECTORS()
H A DLegalizeDAG.cpp2307 (DestVT.bitsLE(MVT::f64) || in ExpandLegalINT_TO_FP()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1259 cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32)) { in selectSExti32()
1282 cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32)) { in selectZExti32()
H A DRISCVInstrInfo.td880 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
884 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
H A DRISCVISelLowering.cpp1521 assert((ViaIntVT.bitsLE(XLenVT) || in lowerBUILD_VECTOR()
1524 if (ViaIntVT.bitsLE(XLenVT) || isInt<32>(SplatValue)) { in lowerBUILD_VECTOR()
1685 if (Scalar.getValueType().bitsLE(XLenVT)) { in lowerScalarSplat()
3366 if (Scalar.getValueType().bitsLE(XLenVT)) { in LowerINTRINSIC_WO_CHAIN()
3415 if (Scalar.getValueType().bitsLE(XLenVT)) in LowerINTRINSIC_WO_CHAIN()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DMachineValueType.h1087 bool bitsLE(MVT VT) const { in bitsLE() function
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1188 assert(VT.bitsLE(MVT::i32)); in LowerSTORE()
H A DAMDGPUISelLowering.cpp3320 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16)) in performMulCombine()
H A DSIISelLowering.cpp1572 VT.getScalarType().bitsLE(MVT::i16)) in getPreferredVectorAction()
5091 return Op.getValueType().bitsLE(VT) ? in getFPExtOrFPRound()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1364 return VT.bitsLE(MVT::i32) || Subtarget.atLeastM68020(); in decomposeMulByConstant()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp24884 assert(MaskVT.bitsLE(Mask.getSimpleValueType()) && "Unexpected mask size!"); in getMaskNode()
28134 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!"); in LowerScalarVariableShift()