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Searched refs:_reg_write_2 (Results 1 – 25 of 28) sorted by relevance

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/netbsd-src/sys/arch/mmeye/mmeye/
H A Dmachdep.c369 _reg_write_2(SH3_BCR1, 0x1010); in InitializeBsc()
378 _reg_write_2(SH3_BCR1, 0x1013); in InitializeBsc()
390 _reg_write_2(SH3_BCR2, 0x2af4); in InitializeBsc()
399 _reg_write_2(SH3_BCR2, 0x16f4); in InitializeBsc()
406 _reg_write_2(SH3_WCR1, 0x3fff); in InitializeBsc()
417 _reg_write_2(SH3_WCR2, 0x4bdd); in InitializeBsc()
428 _reg_write_2(SH3_WCR2, 0xabfd); in InitializeBsc()
438 _reg_write_2(SH3_MCR, 0x6135); in InitializeBsc()
442 _reg_write_2(SH3_DCR, 0x0000); in InitializeBsc()
449 _reg_write_2(SH3_PCR, 0x00ff); in InitializeBsc()
[all …]
/netbsd-src/sys/arch/hpcsh/dev/
H A Dpfckbd.c310 _reg_write_2(SH7709_PDCR, dc | scan[column].dc); in pfckbd_callout_hp()
311 _reg_write_2(SH7709_PECR, ec | scan[column].ec); in pfckbd_callout_hp()
331 _reg_write_2(SH7709_PDCR, dc | (0x5555 & PFCKBD_HP_PDCR_MASK)); in pfckbd_callout_hp()
332 _reg_write_2(SH7709_PECR, ec | (0x5555 & PFCKBD_HP_PECR_MASK)); in pfckbd_callout_hp()
408 _reg_write_2(SH7709_PCCR, cc | scan[i].cc); in pfckbd_callout_hitachi()
409 _reg_write_2(SH7709_PDCR, dc | scan[i].dc); in pfckbd_callout_hitachi()
410 _reg_write_2(SH7709_PECR, ec | scan[i].ec); in pfckbd_callout_hitachi()
433 _reg_write_2(SH7709_PCCR, cc | (0x5555 & PFCKBD_HITACHI_PCCR_MASK)); in pfckbd_callout_hitachi()
434 _reg_write_2(SH7709_PDCR, dc | (0x5555 & PFCKBD_HITACHI_PDCR_MASK)); in pfckbd_callout_hitachi()
435 _reg_write_2(SH7709_PECR, ec | (0x5555 & PFCKBD_HITACHI_PECR_MASK)); in pfckbd_callout_hitachi()
[all …]
/netbsd-src/sys/arch/evbsh3/evbsh3/
H A Dmachdep.c366 _reg_write_2(SH3_BCR1, BSC_BCR1_VAL); in InitializeBsc()
378 _reg_write_2(SH_(BCR2), BSC_BCR2_VAL); in InitializeBsc()
386 _reg_write_2(SH3_WCR1, BSC_WCR1_VAL); in InitializeBsc()
401 _reg_write_2(SH3_WCR2, BSC_WCR2_VAL); in InitializeBsc()
418 _reg_write_2(SH3_MCR, BSC_MCR_VAL); in InitializeBsc()
431 _reg_write_2(0x1a000000, 0); /* ADDSET */ in InitializeBsc()
433 _reg_write_2(0x18000000, 0); /* ADDRST */ in InitializeBsc()
443 _reg_write_2(SH_(PCR), BSC_PCR_VAL); in InitializeBsc()
453 _reg_write_2(SH_(RTCSR), BSC_RTCSR_VAL); in InitializeBsc()
460 _reg_write_2(SH_(RTCNT), BSC_RTCNT_VAL); in InitializeBsc()
[all …]
/netbsd-src/sys/arch/sh3/sh3/
H A Dclock.c119 _reg_write_2(SH_(TCR0), 0); in sh_clock_init()
120 _reg_write_2(SH_(TCR1), 0); in sh_clock_init()
121 _reg_write_2(SH_(TCR2), 0); in sh_clock_init()
134 _reg_write_2(SH_(TCR0), TCR_TPSC_P16); in sh_clock_init()
138 _reg_write_2(SH_(TCR0), in sh_clock_init()
168 _reg_write_2(SH_(TCR1), TCR_TPSC_P4); in sh_clock_init()
247 _reg_write_2(SH_(TCR0), TCR_UNIE | TCR_TPSC_P16); in cpu_initclocks()
250 _reg_write_2(SH_(TCR0), TCR_UNIE | in cpu_initclocks()
267 _reg_write_2(SH_(TCR1), TCR_UNIE | TCR_TPSC_P4); in cpu_initclocks()
273 _reg_write_2(SH_(TCR2), TCR_TPSC_P4); in cpu_initclocks()
H A Dinterrupt.c77 _reg_write_2(SH7709_IPRC, 0); in intc_init()
78 _reg_write_2(SH7709_IPRD, 0); in intc_init()
79 _reg_write_2(SH7709_IPRE, 0); in intc_init()
84 _reg_write_2(SH3_IPRA, 0); in intc_init()
85 _reg_write_2(SH3_IPRB, 0); in intc_init()
97 _reg_write_2(SH4_IPRD, 0); in intc_init()
100 _reg_write_2(SH4_IPRA, 0); in intc_init()
101 _reg_write_2(SH4_IPRB, 0); in intc_init()
102 _reg_write_2(SH4_IPRC, 0); in intc_init()
356 _reg_write_2(iprreg, r); in intc_intr_priority()
H A Dsh3_machdep.c195 _reg_write_2(SH_(BBRA), 0); /* disable channel A */ in sh_cpu_init()
196 _reg_write_2(SH_(BBRB), 0); /* disable channel B */ in sh_cpu_init()
212 _reg_write_2(SH4_BRCR, UBC_CTL_A_AFTER_INSN); in sh_cpu_init()
/netbsd-src/sys/arch/playstation2/dev/
H A Dsbus.c255 _reg_write_2(SBUS_PCMCIA_CSC1_REG16, 0xffff); in sbus_type2_pcmcia_intr_clear()
262 _reg_write_2(SBUS_PCMCIA_TIMR_REG16, 0); in sbus_type2_pcmcia_intr_enable()
269 _reg_write_2(SBUS_PCMCIA_TIMR_REG16, 1); in sbus_type2_pcmcia_intr_disable()
277 _reg_write_2(SBUS_PCMCIA_TIMR_REG16, 1); in sbus_type2_pcmcia_intr_reinstall()
278 _reg_write_2(SBUS_PCMCIA_TIMR_REG16, r); in sbus_type2_pcmcia_intr_reinstall()
292 _reg_write_2(SBUS_PCMCIA3_TIMR_REG16, 0); in sbus_type3_pcmcia_intr_enable()
299 _reg_write_2(SBUS_PCMCIA3_TIMR_REG16, 1); in sbus_type3_pcmcia_intr_disable()
307 _reg_write_2(SBUS_PCMCIA3_TIMR_REG16, 1); in sbus_type3_pcmcia_intr_reinstall()
308 _reg_write_2(SBUS_PCMCIA3_TIMR_REG16, r); in sbus_type3_pcmcia_intr_reinstall()
H A Dif_smap.c176 _reg_write_2(SPD_INTR_ENABLE_REG16, r); in smap_attach()
180 _reg_write_2(SPD_INTR_CLEAR_REG16, SPD_INTR_RXEND | SPD_INTR_TXEND | in smap_attach()
280 _reg_write_2(SPD_INTR_ENABLE_REG16, r); in smap_intr()
289 _reg_write_2(SPD_INTR_CLEAR_REG16, disable); in smap_intr()
293 _reg_write_2(SPD_INTR_CLEAR_REG16, SPD_INTR_TXEND); in smap_intr()
300 _reg_write_2(SPD_INTR_CLEAR_REG16, SPD_INTR_RXEND); in smap_intr()
352 _reg_write_2(SMAP_RXFIFO_PTR_REG16, d->ptr & 0x3ffc); in smap_rxeof()
400 _reg_write_2(SPD_INTR_ENABLE_REG16, r16); in smap_rxeof()
504 _reg_write_2(SMAP_TXFIFO_PTR_REG16, fifop); in smap_start()
531 _reg_write_2(SPD_INTR_ENABLE_REG16, r16); in smap_start()
[all …]
H A Dspd.c107 _reg_write_2(SPD_INTR_ENABLE_REG16, 0); in spd_attach()
108 _reg_write_2(SPD_INTR_CLEAR_REG16, _reg_read_2(SPD_INTR_STATUS_REG16)); in spd_attach()
152 _reg_write_2(SPD_INTR_ENABLE_REG16, 0); in spd_intr()
153 _reg_write_2(SPD_INTR_ENABLE_REG16, r); in spd_intr()
H A Dwdc_spd.c238 _reg_write_2(SPD_INTR_ENABLE_REG16, r); in __wdc_spd_enable()
248 _reg_write_2(SPD_INTR_ENABLE_REG16, r); in __wdc_spd_disable()
H A Demac3.c89 _reg_write_2(a_, (v >> 16) & 0xffff); in _emac3_reg_write_4()
90 _reg_write_2(a_ + 2, v & 0xffff); in _emac3_reg_write_4()
/netbsd-src/sys/arch/evbsh3/ap_ms104_sh4/
H A Dap_ms104_sh4.c63 _reg_write_2(SH4_GPIOIC, 0); in gpio_intr_init()
64 _reg_write_2(SH4_PDTRA, 0); in gpio_intr_init()
66 _reg_write_2(SH4_PDTRB, 0); in gpio_intr_init()
73 _reg_write_2(SH4_PDTRA, (1 << GPIO_PIN_CARD_PON) in gpio_intr_init()
107 _reg_write_2(SH4_GPIOIC, reg); in gpio_intr_establish()
129 _reg_write_2(SH4_GPIOIC, reg); in gpior_intr_disestablish()
158 _reg_write_2(SH4_GPIOIC, r); in gpio_intr()
H A Drs5c316_mainbus.c125 _reg_write_2(SH4_PDTRA, reg); in rtc_ce()
140 _reg_write_2(SH4_PDTRA, reg); in rtc_clk()
182 _reg_write_2(SH4_PDTRA, reg); in rtc_write()
H A Dshpcmcia.c815 _reg_write_2(SH4_PDTRA, reg); in shpcmcia_chip_socket_enable()
824 _reg_write_2(SH4_PDTRA, reg); in shpcmcia_chip_socket_enable()
829 _reg_write_2(SH4_PDTRA, reg); in shpcmcia_chip_socket_enable()
844 _reg_write_2(SH4_PDTRA, reg); in shpcmcia_chip_socket_disable()
849 _reg_write_2(SH4_PDTRA, reg); in shpcmcia_chip_socket_disable()
854 _reg_write_2(SH4_PDTRA, reg); in shpcmcia_chip_socket_disable()
/netbsd-src/sys/arch/landisk/landisk/
H A Dmachdep.c404 _reg_write_2(SH4_BCR2, BSC_BCR2_VAL); in InitializeBsc()
409 _reg_write_2(SH4_BCR3, BSC_BCR3_VAL); in InitializeBsc()
462 _reg_write_2(SH4_PCR, BSC_PCR_VAL); in InitializeBsc()
472 _reg_write_2(SH4_RTCSR, BSC_RTCSR_VAL); in InitializeBsc()
479 _reg_write_2(SH4_RTCNT, BSC_RTCNT_VAL); in InitializeBsc()
483 _reg_write_2(SH4_RTCOR, BSC_RTCOR_VAL); in InitializeBsc()
487 _reg_write_2(SH4_RFCR, BSC_RFCR_VAL); in InitializeBsc()
494 _reg_write_2(SH4_FRQCR, FRQCR_VAL); in InitializeBsc()
/netbsd-src/sys/arch/evbsh3/t_sh7706lan/
H A Dt_sh7706lan.c47 _reg_write_2(SH7709_PHCR, 0x2800); in machine_init()
52 _reg_write_2(SH7709_SCPCR, reg); in machine_init()
55 _reg_write_2(SH7709_ICR1, 0x0aaa); in machine_init()
61 _reg_write_2(SH3_BCR2, reg); in machine_init()
H A Dssumci.c120 _reg_write_2((reg), _r); \
136 _reg_write_2((reg), _r); \
H A Dscimci.c118 _reg_write_2((reg), _r); \
134 _reg_write_2((reg), _r); \
/netbsd-src/sys/arch/hpc/stand/hpcboot/sh3/dev/
H A Dsh4_dev.cpp113 _reg_write_2(SH4_IPRA, 0); in icu_dump()
114 _reg_write_2(SH4_IPRB, 0); in icu_dump()
115 _reg_write_2(SH4_IPRC, 0); in icu_dump()
170 _reg_write_2(a, ~_reg_read_2(a) & 0xffff); in mq100_dump()
/netbsd-src/sys/arch/mmeye/stand/boot/
H A Dclock.c41 _reg_write_2(SH_(TCR0), TCR_TPSC_P4); in tmu_init()
/netbsd-src/sys/arch/playstation2/ee/
H A Deevar.h47 #define _reg_write_2(a, v) __write_2(a, v) macro
/netbsd-src/sys/arch/sh3/include/
H A Ddevreg.h43 #define _reg_write_2(a, v) \ macro
/netbsd-src/sys/arch/landisk/stand/boot/
H A Ddelay.c99 _reg_write_2(TCR, TCR_TPSC); in tick_init()
/netbsd-src/sys/arch/hpc/stand/hpcboot/
H A Dhpcboot.h128 #define _reg_write_2(a, v) (*(volatile uint16_t *)(a) = (v)) macro
/netbsd-src/sys/arch/sh3/dev/
H A Drtc.c244 _reg_write_2(SH4_RYRCNT, year); in rtc_settime_ymdhms()

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