1*8aaa114dSandvar /* $NetBSD: devreg.h,v 1.7 2021/10/06 20:36:58 andvar Exp $ */ 2bbc655c4Such 3bbc655c4Such /*- 4bbc655c4Such * Copyright (c) 2002 The NetBSD Foundation, Inc. 5bbc655c4Such * All rights reserved. 6bbc655c4Such * 7bbc655c4Such * Redistribution and use in source and binary forms, with or without 8bbc655c4Such * modification, are permitted provided that the following conditions 9bbc655c4Such * are met: 10bbc655c4Such * 1. Redistributions of source code must retain the above copyright 11bbc655c4Such * notice, this list of conditions and the following disclaimer. 12bbc655c4Such * 2. Redistributions in binary form must reproduce the above copyright 13bbc655c4Such * notice, this list of conditions and the following disclaimer in the 14bbc655c4Such * documentation and/or other materials provided with the distribution. 15bbc655c4Such * 16bbc655c4Such * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17bbc655c4Such * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18bbc655c4Such * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19bbc655c4Such * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20bbc655c4Such * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21bbc655c4Such * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22bbc655c4Such * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23bbc655c4Such * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24bbc655c4Such * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25bbc655c4Such * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26bbc655c4Such * POSSIBILITY OF SUCH DAMAGE. 27bbc655c4Such */ 28bbc655c4Such 29bbc655c4Such #ifndef _SH3_DEVREG_H_ 30bbc655c4Such #define _SH3_DEVREG_H_ 31bbc655c4Such /* 32*8aaa114dSandvar * SH embedded device register defines. 33bbc655c4Such */ 34bbc655c4Such 35bbc655c4Such /* 36bbc655c4Such * Access method 37bbc655c4Such */ 38530e77afSuwe #define _reg_read_1(a) (*(volatile uint8_t *)((vaddr_t)(a))) 39530e77afSuwe #define _reg_read_2(a) (*(volatile uint16_t *)((vaddr_t)(a))) 40530e77afSuwe #define _reg_read_4(a) (*(volatile uint32_t *)((vaddr_t)(a))) 41bbc655c4Such #define _reg_write_1(a, v) \ 42530e77afSuwe (*(volatile uint8_t *)(a) = (uint8_t)(v)) 43bbc655c4Such #define _reg_write_2(a, v) \ 44530e77afSuwe (*(volatile uint16_t *)(a) = (uint16_t)(v)) 45bbc655c4Such #define _reg_write_4(a, v) \ 46530e77afSuwe (*(volatile uint32_t *)(a) = (uint32_t)(v)) 47d7fe782bStsutsui #define _reg_bset_1(a, v) \ 48530e77afSuwe (*(volatile uint8_t *)(a) |= (uint8_t)(v)) 49d7fe782bStsutsui #define _reg_bset_2(a, v) \ 50530e77afSuwe (*(volatile uint16_t *)(a) |= (uint16_t)(v)) 51d7fe782bStsutsui #define _reg_bset_4(a, v) \ 52530e77afSuwe (*(volatile uint32_t *)(a) |= (uint32_t)(v)) 53d7fe782bStsutsui #define _reg_bclr_1(a, v) \ 54530e77afSuwe (*(volatile uint8_t *)(a) &= ~(uint8_t)(v)) 55d7fe782bStsutsui #define _reg_bclr_2(a, v) \ 56530e77afSuwe (*(volatile uint16_t *)(a) &= ~(uint16_t)(v)) 57d7fe782bStsutsui #define _reg_bclr_4(a, v) \ 58530e77afSuwe (*(volatile uint32_t *)(a) &= ~(uint32_t)(v)) 59bbc655c4Such 60bbc655c4Such /* 61bbc655c4Such * Register address. 62bbc655c4Such */ 63bbc655c4Such #if defined(SH3) && defined(SH4) 64bbc655c4Such #define SH_(x) __sh_ ## x 65bbc655c4Such #elif defined(SH3) 66bbc655c4Such #define SH_(x) SH3_ ## x 67bbc655c4Such #elif defined(SH4) 68bbc655c4Such #define SH_(x) SH4_ ## x 69bbc655c4Such #endif 70bbc655c4Such 71bbc655c4Such #ifndef _LOCORE 72bbc655c4Such /* Initialize register address for SH3 && SH4 kernel. */ 73bbc655c4Such void sh_devreg_init(void); 74bbc655c4Such #endif 75bbc655c4Such #endif /* !_SH3_DEVREG_H_ */ 76