Home
last modified time | relevance | path

Searched refs:VecVT (Results 1 – 25 of 27) sorted by relevance

12

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1118 MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, in decomposeSubvectorInsertExtractToSubRegs() argument
1124 unsigned VecRegClassID = getRegClassIDForVecVT(VecVT); in decomposeSubvectorInsertExtractToSubRegs()
1136 VecVT = VecVT.getHalfNumVectorElementsVT(); in decomposeSubvectorInsertExtractToSubRegs()
1138 InsertExtractIdx >= VecVT.getVectorElementCount().getKnownMinValue(); in decomposeSubvectorInsertExtractToSubRegs()
1140 getSubregIndexByMVT(VecVT, IsHi)); in decomposeSubvectorInsertExtractToSubRegs()
1142 InsertExtractIdx -= VecVT.getVectorElementCount().getKnownMinValue(); in decomposeSubvectorInsertExtractToSubRegs()
1279 getDefaultVLOps(MVT VecVT, MVT ContainerVT, SDLoc DL, SelectionDAG &DAG, in getDefaultVLOps() argument
1283 SDValue VL = VecVT.isFixedLengthVector() in getDefaultVLOps()
1284 ? DAG.getConstant(VecVT.getVectorNumElements(), DL, XLenVT) in getDefaultVLOps()
1293 getDefaultScalableVLOps(MVT VecVT, SDLoc DL, SelectionDAG &DAG, in getDefaultScalableVLOps() argument
[all …]
H A DRISCVISelLowering.h476 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp373 EVT VecVT = N->getValueType(0); in ExpandOp_BUILD_VECTOR() local
374 unsigned NumElts = VecVT.getVectorNumElements(); in ExpandOp_BUILD_VECTOR()
379 assert(OldVT == VecVT.getVectorElementType() && in ExpandOp_BUILD_VECTOR()
400 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); in ExpandOp_BUILD_VECTOR()
411 EVT VecVT = N->getValueType(0); in ExpandOp_INSERT_VECTOR_ELT() local
412 unsigned NumElts = VecVT.getVectorNumElements(); in ExpandOp_INSERT_VECTOR_ELT()
419 assert(OldEVT == VecVT.getVectorElementType() && in ExpandOp_INSERT_VECTOR_ELT()
442 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); in ExpandOp_INSERT_VECTOR_ELT()
H A DLegalizeVectorTypes.cpp1277 EVT VecVT = Vec.getValueType(); in SplitVecRes_INSERT_SUBVECTOR() local
1280 unsigned VecElems = VecVT.getVectorMinNumElements(); in SplitVecRes_INSERT_SUBVECTOR()
1295 if (VecVT.isScalableVector() == SubVecVT.isScalableVector() && in SplitVecRes_INSERT_SUBVECTOR()
1305 Align SmallestAlign = DAG.getReducedAlign(VecVT, /*UseABI=*/false); in SplitVecRes_INSERT_SUBVECTOR()
1307 DAG.CreateStackTemporary(VecVT.getStoreSize(), SmallestAlign); in SplitVecRes_INSERT_SUBVECTOR()
1316 SDValue SubVecPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx); in SplitVecRes_INSERT_SUBVECTOR()
1517 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, ResNE); in UnrollVectorOp_StrictFP() local
1518 return DAG.getBuildVector(VecVT, dl, Scalars); in UnrollVectorOp_StrictFP()
1591 EVT VecVT = Vec.getValueType(); in SplitVecRes_INSERT_VECTOR_ELT() local
1592 EVT EltVT = VecVT.getVectorElementType(); in SplitVecRes_INSERT_VECTOR_ELT()
[all …]
H A DDAGCombiner.cpp18511 EVT VecVT = VecOp.getValueType(); in visitEXTRACT_VECTOR_ELT() local
18523 return VecVT.isInteger() ? DAG.getAnyExtOrTrunc(Elt, DL, ScalarVT) : Elt; in visitEXTRACT_VECTOR_ELT()
18545 if (IndexC && VecVT.isFixedLengthVector() && in visitEXTRACT_VECTOR_ELT()
18546 IndexC->getAPIntValue().uge(VecVT.getVectorNumElements())) in visitEXTRACT_VECTOR_ELT()
18552 TLI.isTypeLegal(VecVT) && in visitEXTRACT_VECTOR_ELT()
18553 (VecOp.hasOneUse() || TLI.aggressivelyPreferBuildVectorSources(VecVT))) { in visitEXTRACT_VECTOR_ELT()
18555 VecVT.isFixedLengthVector()) && in visitEXTRACT_VECTOR_ELT()
18570 if (VecVT.isScalableVector()) in visitEXTRACT_VECTOR_ELT()
18576 unsigned NumElts = VecVT.getVectorNumElements(); in visitEXTRACT_VECTOR_ELT()
18577 unsigned VecEltBitWidth = VecVT.getScalarSizeInBits(); in visitEXTRACT_VECTOR_ELT()
[all …]
H A DLegalizeDAG.cpp1362 EVT VecVT = Vec.getValueType(); in ExpandExtractFromVectorThroughStack() local
1366 StackPtr = DAG.CreateStackTemporary(VecVT); in ExpandExtractFromVectorThroughStack()
1371 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx); in ExpandExtractFromVectorThroughStack()
1381 VecVT.getVectorElementType()); in ExpandExtractFromVectorThroughStack()
1405 EVT VecVT = Vec.getValueType(); in ExpandInsertToVectorThroughStack() local
1406 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); in ExpandInsertToVectorThroughStack()
1415 SDValue SubStackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx); in ExpandInsertToVectorThroughStack()
H A DTargetLowering.cpp824 EVT VecVT = Vec.getValueType(); in SimplifyMultipleUseDemandedBits() local
825 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements()) && in SimplifyMultipleUseDemandedBits()
1009 EVT VecVT = Vec.getValueType(); in SimplifyDemandedBits() local
1014 if (CIdx && CIdx->getAPIntValue().ult(VecVT.getVectorNumElements())) { in SimplifyDemandedBits()
7777 EVT VecVT, in clampDynamicVectorIndex() argument
7779 if (!VecVT.isScalableVector() && isa<ConstantSDNode>(Idx)) in clampDynamicVectorIndex()
7783 unsigned NElts = VecVT.getVectorMinNumElements(); in clampDynamicVectorIndex()
7784 if (VecVT.isScalableVector()) { in clampDynamicVectorIndex()
7806 SDValue VecPtr, EVT VecVT, in getVectorElementPointer() argument
7812 EVT EltVT = VecVT.getVectorElementType(); in getVectorElementPointer()
[all …]
H A DSelectionDAG.cpp3407 EVT VecVT = InVec.getValueType(); in computeKnownBits() local
3409 if (VecVT.isScalableVector()) in computeKnownBits()
3411 const unsigned EltBitWidth = VecVT.getScalarSizeInBits(); in computeKnownBits()
3412 const unsigned NumSrcElts = VecVT.getVectorNumElements(); in computeKnownBits()
4070 EVT VecVT = InVec.getValueType(); in ComputeNumSignBits() local
4072 if (VecVT.isScalableVector()) in ComputeNumSignBits()
4076 const unsigned NumSrcElts = VecVT.getVectorNumElements(); in ComputeNumSignBits()
9982 EVT VecVT = EVT::getVectorVT(*getContext(), EltVT, ResNE); in UnrollVectorOp() local
9983 return getBuildVector(VecVT, dl, Scalars); in UnrollVectorOp()
H A DLegalizeFloatTypes.cpp2333 EVT VecVT = Vec->getValueType(0); in PromoteFloatRes_EXTRACT_VECTOR_ELT() local
2334 EVT EltVT = VecVT.getVectorElementType(); in PromoteFloatRes_EXTRACT_VECTOR_ELT()
2338 switch (getTypeAction(VecVT)) { in PromoteFloatRes_EXTRACT_VECTOR_ELT()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4177 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC, in getVCmpInst() argument
4182 if (VecVT.isFloatingPoint()) { in getVCmpInst()
4205 if (VecVT == MVT::v4f32) in getVCmpInst()
4207 else if (VecVT == MVT::v2f64) in getVCmpInst()
4212 if (VecVT == MVT::v4f32) in getVCmpInst()
4214 else if (VecVT == MVT::v2f64) in getVCmpInst()
4219 if (VecVT == MVT::v4f32) in getVCmpInst()
4221 else if (VecVT == MVT::v2f64) in getVCmpInst()
4249 if (VecVT == MVT::v16i8) in getVCmpInst()
4251 else if (VecVT == MVT::v8i16) in getVCmpInst()
[all …]
H A DPPCISelLowering.cpp8311 EVT VecVT = Vec.getValueType(); in widenVec() local
8312 assert(VecVT.isVector() && "Expected a vector type."); in widenVec()
8313 assert(VecVT.getSizeInBits() < 128 && "Vector is already full width."); in widenVec()
8315 EVT EltVT = VecVT.getVectorElementType(); in widenVec()
8319 unsigned NumConcat = WideNumElts / VecVT.getVectorNumElements(); in widenVec()
8322 SDValue UndefVec = DAG.getUNDEF(VecVT); in widenVec()
8916 EVT VecVT = V->getValueType(0); in haveEfficientBuildVectorPattern() local
8917 bool RightType = VecVT == MVT::v2f64 || in haveEfficientBuildVectorPattern()
8918 (HasP8Vector && VecVT == MVT::v4f32) || in haveEfficientBuildVectorPattern()
8919 (HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32)); in haveEfficientBuildVectorPattern()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp737 VecVT = MVT::getVectorVT(MVT::getIntegerVT(8), 16); in isVectorConstantLegal()
750 VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize), in isVectorConstantLegal()
763 VecVT = MVT::getVectorVT(MVT::getIntegerVT(SplatBitSize), in isVectorConstantLegal()
5249 EVT VecVT = Op0.getValueType(); in lowerEXTRACT_VECTOR_ELT() local
5254 unsigned Mask = VecVT.getVectorNumElements() - 1; in lowerEXTRACT_VECTOR_ELT()
5261 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements()); in lowerEXTRACT_VECTOR_ELT()
5724 EVT VecVT, SDValue Op, in combineExtract() argument
5731 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize(); in combineExtract()
5817 if (Op.getValueType() != VecVT) { in combineExtract()
5818 Op = DAG.getNode(ISD::BITCAST, DL, VecVT, Op); in combineExtract()
[all …]
H A DSystemZISelLowering.h634 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
721 MVT VecVT; member
H A DSystemZISelDAGToDAG.cpp1156 assert(VCI.VecVT.getSizeInBits() == 128 && "Expected a vector type"); in loadVectorConstant()
1162 SDValue Op = CurDAG->getNode(VCI.Opcode, DL, VCI.VecVT, Ops); in loadVectorConstant()
1164 if (VCI.VecVT == VT.getSimpleVT()) in loadVectorConstant()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3557 MVT VecVT = MVT::Other; in forwardMustTailParameters() local
3562 VecVT = MVT::v16f32; in forwardMustTailParameters()
3564 VecVT = MVT::v8f32; in forwardMustTailParameters()
3566 VecVT = MVT::v4f32; in forwardMustTailParameters()
3572 if (VecVT != MVT::Other) in forwardMustTailParameters()
3573 RegParmTypes.push_back(VecVT); in forwardMustTailParameters()
5352 EVT VecVT = VecOp.getValueType(); in shouldScalarizeBinop() local
5353 if (!isOperationLegalOrCustomOrPromote(Opc, VecVT)) in shouldScalarizeBinop()
5358 EVT ScalarVT = VecVT.getScalarType(); in shouldScalarizeBinop()
8671 MVT VecVT = MVT::getVectorVT(VecSVT, VT.getSizeInBits() / LoadSizeInBits); in EltsFromConsecutiveLoads() local
[all …]
H A DX86ISelDAGToDAG.cpp424 MVT VecVT = N->getOperand(0).getSimpleValueType(); in getExtractVEXTRACTImmediate() local
425 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL); in getExtractVEXTRACTImmediate()
432 MVT VecVT = N->getSimpleValueType(0); in getInsertVINSERTImmediate() local
433 return getI8Imm((Index * VecVT.getScalarSizeInBits()) / VecWidth, DL); in getInsertVINSERTImmediate()
1124 MVT VecVT = VT == MVT::f64 ? MVT::v2f64 : MVT::v4f32; in PreprocessISelDAG() local
1126 SDValue Op0 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1128 SDValue Op1 = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, in PreprocessISelDAG()
1133 EVT IntVT = EVT(VecVT).changeVectorElementTypeToInteger(); in PreprocessISelDAG()
1145 Res = CurDAG->getNode(ISD::BITCAST, dl, VecVT, Res); in PreprocessISelDAG()
1147 Res = CurDAG->getNode(N->getOpcode(), dl, VecVT, Op0, Op1); in PreprocessISelDAG()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp5376 EVT VecVT = Vec.getValueType(); in lowerINSERT_SUBVECTOR() local
5378 EVT EltVT = VecVT.getVectorElementType(); in lowerINSERT_SUBVECTOR()
5386 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt, in lowerINSERT_SUBVECTOR()
5397 EVT VecVT = Vec.getValueType(); in lowerINSERT_VECTOR_ELT() local
5398 EVT EltVT = VecVT.getVectorElementType(); in lowerINSERT_VECTOR_ELT()
5399 unsigned VecSize = VecVT.getSizeInBits(); in lowerINSERT_VECTOR_ELT()
5405 unsigned NumElts = VecVT.getVectorNumElements(); in lowerINSERT_VECTOR_ELT()
5433 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat); in lowerINSERT_VECTOR_ELT()
5447 DAG.getSplatBuildVector(VecVT, SL, InsVal)); in lowerINSERT_VECTOR_ELT()
5465 return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI); in lowerINSERT_VECTOR_ELT()
[all …]
H A DAMDGPUISelLowering.h188 bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
H A DR600ISelLowering.cpp675 EVT VecVT = Vector.getValueType(); in vectorToVerticalVector() local
676 EVT EltVT = VecVT.getVectorElementType(); in vectorToVerticalVector()
679 for (unsigned i = 0, e = VecVT.getVectorNumElements(); i != e; ++i) { in vectorToVerticalVector()
684 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp5926 EVT VecVT = EVT::getVectorVT( in CombineVMOVDRRCandidateWithVecOp() local
5929 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc); in CombineVMOVDRRCandidateWithVecOp()
7632 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), IVT, NumElts); in LowerBUILD_VECTOR() local
7633 SDValue Val = DAG.getBuildVector(VecVT, dl, Ops); in LowerBUILD_VECTOR()
7690 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); in LowerBUILD_VECTOR() local
7694 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); in LowerBUILD_VECTOR()
8506 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); in LowerVECTOR_SHUFFLE() local
8507 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); in LowerVECTOR_SHUFFLE()
8508 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); in LowerVECTOR_SHUFFLE()
8519 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); in LowerVECTOR_SHUFFLE()
[all …]
H A DARMISelDAGToDAG.cpp4117 EVT VecVT = N->getValueType(0); in Select() local
4118 EVT EltVT = VecVT.getVectorElementType(); in Select()
4119 unsigned NumElts = VecVT.getVectorNumElements(); in Select()
4123 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
4129 N, createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
4134 createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1), in Select()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2791 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const { in aggressivelyPreferBuildVectorSources() argument
4479 SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp6736 EVT VecVT; in LowerFCOPYSIGN() local
6742 VecVal1 = DAG.getTargetInsertSubreg(Idx, DL, VecVT, in LowerFCOPYSIGN()
6743 DAG.getUNDEF(VecVT), In1); in LowerFCOPYSIGN()
6744 VecVal2 = DAG.getTargetInsertSubreg(Idx, DL, VecVT, in LowerFCOPYSIGN()
6745 DAG.getUNDEF(VecVT), In2); in LowerFCOPYSIGN()
6747 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1); in LowerFCOPYSIGN()
6748 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2); in LowerFCOPYSIGN()
6753 VecVT = (VT == MVT::v2f32 ? MVT::v2i32 : MVT::v4i32); in LowerFCOPYSIGN()
6757 VecVT = MVT::v2i64; in LowerFCOPYSIGN()
6766 VecVT = (VT == MVT::v4f16 ? MVT::v4i16 : MVT::v8i16); in LowerFCOPYSIGN()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEISelLowering.cpp88 for (MVT VecVT : AllVectorVTs) in initRegisterClasses() local
89 addRegisterClass(VecVT, &VE::V64RegClass); in initRegisterClasses()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2567 EVT VecVT = EVT::getVectorVT(F->getContext(), LoadVT, NumElts); in LowerFormalArguments() local
2574 DAG.getLoad(VecVT, dl, Root, VecAddr, in LowerFormalArguments()

12