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Searched refs:VSELECT (Results 1 – 25 of 25) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp106 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
167 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
352 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
397 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
711 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); in performORCombine()
1046 case ISD::VSELECT: in PerformDAGCombine()
1618 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1633 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1638 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1641 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h678 VSELECT, enumerator
H A DBasicTTIImpl.h1035 ISD = ISD::VSELECT;
H A DSelectionDAG.h1074 auto Opcode = Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp184 setOperationAction(ISD::VSELECT, T, Custom); in initializeHVXLowering()
270 setTargetDAGCombine(ISD::VSELECT); in initializeHVXLowering()
1719 SDValue VSel = DAG.getNode(ISD::VSELECT, dl, ValTy, Mask, Load, Thru); in LowerHvxMaskedOp()
2088 case ISD::VSELECT: in LowerHvxOperation()
2245 case ISD::VSELECT: { in PerformHvxDAGCombine()
2251 return DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, Ops[2], Ops[1]); in PerformHvxDAGCombine()
H A DHexagonISelLowering.cpp1749 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom); in HexagonTargetLowering()
1750 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
1803 setTargetDAGCombine(ISD::VSELECT); in HexagonTargetLowering()
3169 case ISD::VSELECT: return LowerVSELECT(Op, DAG); in LowerOperation()
3255 } else if (Opc == ISD::VSELECT) { in PerformDAGCombine()
3263 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, in PerformDAGCombine()
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dimx7-mba7.dtsi448 /* VSELECT */
H A Dimx6ul-14x14-evk.dtsi605 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; in ScalarizeVectorResult()
628 case ISD::VSELECT: in ScalarizeVectorOperand()
915 case ISD::VSELECT: in SplitVectorResult()
2178 case ISD::VSELECT: in SplitVectorOperand()
2281 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); in SplitVecOp_VSELECT()
2283 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); in SplitVecOp_VSELECT()
2992 case ISD::VSELECT: in WidenVectorResult()
4244 if (N->getOpcode() != ISD::VSELECT) in WidenVSELECTMask()
4537 case ISD::VSELECT: Res = WidenVecOp_VSELECT(N); break; in WidenVectorOperand()
H A DLegalizeVectorOps.cpp398 case ISD::VSELECT: in LegalizeOp()
754 case ISD::VSELECT: in Expand()
H A DSelectionDAGDumper.cpp282 case ISD::VSELECT: return "vselect"; in getOperationName()
H A DTargetLowering.cpp2675 case ISD::VSELECT: { in SimplifyDemandedVectorElts()
5651 if (isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) { in prepareUREMEqFold()
5656 return DAG.getNode(ISD::VSELECT, DL, SETCCVT, TautologicalInvertedChannels, in prepareUREMEqFold()
5915 !isOperationLegalOrCustom(ISD::VSELECT, VT)) in prepareSREMEqFold()
5942 DAG.getNode(ISD::VSELECT, DL, VT, DivisorIsIntMin, MaskedIsZero, Fold); in prepareSREMEqFold()
7946 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandIntMINMAX()
7997 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandAddSubSat()
H A DLegalizeIntegerTypes.cpp77 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; in PromoteIntegerResult()
1048 return DAG.getNode(ISD::VSELECT, SDLoc(N), in PromoteIntRes_VSELECT()
1499 case ISD::VSELECT: in PromoteIntegerOperand()
1758 if (N->getOpcode() == ISD::VSELECT) in PromoteIntOp_SELECT()
H A DSelectionDAG.cpp3055 case ISD::VSELECT: in computeKnownBits()
3850 case ISD::VSELECT: in ComputeNumSignBits()
6030 case ISD::VSELECT: in getNode()
9958 case ISD::VSELECT: in UnrollVectorOp()
H A DDAGCombiner.cpp1665 case ISD::VSELECT: return visitVSELECT(N); in visit()
9367 assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT) && in foldBoolSelectToLogic()
10216 if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) || in tryToFoldExtendSelectLoad()
10607 if (LegalOperations || !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT)) in matchVSelectOpSizesWithSetCC()
10611 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() || in matchVSelectOpSizesWithSetCC()
10634 return DAG.getNode(ISD::VSELECT, DL, VT, SetCC, CastA, CastB); in matchVSelectOpSizesWithSetCC()
22703 Test.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT, in buildSqrtEstimateImpl()
H A DSelectionDAGBuilder.cpp3256 Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT; in visitSelect()
3280 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT); in visitSelect()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp708 setOperationAction(ISD::VSELECT, VT, Custom); in RISCVTargetLowering()
777 setOperationAction(ISD::VSELECT, VT, Custom); in RISCVTargetLowering()
1596 Vec = DAG.getNode(ISD::VSELECT, DL, VT, in lowerBUILD_VECTOR()
1838 return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, V1, V2); in lowerVECTOR_SHUFFLE()
2402 case ISD::VSELECT: in LowerOperation()
3004 return DAG.getNode(ISD::VSELECT, DL, VecVT, Src, SplatTrueVal, SplatZero); in lowerVectorMaskExt()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp189 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
450 setOperationAction(ISD::VSELECT, VT, Expand); in addMVEVectorTypes()
1521 setTargetDAGCombine(ISD::VSELECT); in ARMTargetLowering()
8145 DAG.getNode(ISD::VSELECT, dl, MVT::v16i8, RecastV1, AllOnes, AllZeroes); in PromoteMVEPredVector()
9642 Combo = DAG.getNode(ISD::VSELECT, dl, VT, Mask, NewLoad, PassThru); in LowerMLOAD()
12587 } else if (N->getOpcode() == ISD::VSELECT) { in PerformVQDMULHCombine()
12687 return DCI.DAG.getNode(ISD::VSELECT, SDLoc(N), Type, Cond, RHS, LHS); in PerformVSELECTCombine()
15601 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
15655 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
15763 if (Op->getOpcode() == ISD::VSELECT) in PerformVECREDUCE_ADDCombine()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp904 setTargetDAGCombine(ISD::VSELECT); in AArch64TargetLowering()
1391 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
1525 setOperationAction(ISD::VSELECT, VT, Custom); in addTypeForFixedLengthSVE()
4697 case ISD::VSELECT: in LowerOperation()
7189 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal); in LowerSELECT()
7200 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal); in LowerSELECT()
14109 return DAG.getNode(ISD::VSELECT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
15444 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
16117 case ISD::VSELECT: in PerformDAGCombine()
17840 auto ScalableRes = DAG.getNode(ISD::VSELECT, DL, ContainerVT, in LowerFixedLengthVectorSelectToSVE()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp893 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom); in X86TargetLowering()
991 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
998 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
1153 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in X86TargetLowering()
1418 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
1428 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); in X86TargetLowering()
1488 setOperationAction(ISD::VSELECT, VT, Expand); in X86TargetLowering()
1727 setOperationAction(ISD::VSELECT, VT, Custom); in X86TargetLowering()
1868 setOperationAction(ISD::VSELECT, VT, Expand); in X86TargetLowering()
2013 setTargetDAGCombine(ISD::VSELECT); in X86TargetLowering()
[all …]
H A DX86ISelDAGToDAG.cpp722 (N->getOpcode() == ISD::VSELECT || N->getOpcode() == X86ISD::SELECTS) && in isProfitableToFormMaskedOp()
966 case ISD::VSELECT: { in PreprocessISelDAG()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp445 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
485 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td584 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp779 setOperationAction(ISD::VSELECT, VT, Legal); in PPCTargetLowering()
1339 setTargetDAGCombine(ISD::VSELECT); in PPCTargetLowering()
15380 case ISD::VSELECT: in PerformDAGCombine()
16956 assert((N->getOpcode() == ISD::VSELECT) && "Need VSELECT node here"); in combineVSelect()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp345 setOperationAction(ISD::VSELECT, VT, Legal); in SystemZTargetLowering()