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Searched refs:Rs (Results 1 – 25 of 118) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsics.td12 : Pat <(IntID I32:$Rs),
13 (MI I32:$Rs)>;
16 : Pat <(IntID I32:$Rs, I32:$Rt),
17 (MI I32:$Rs, I32:$Rt)>;
20 : Pat <(IntID I32:$Rs, I64:$Rt),
21 (MI I32:$Rs, I64:$Rt)>;
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
24 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
25 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, timm:$s16),
26 (A2_addi IntRegs:$Rs, imm:$s16)>;
[all …]
H A DHexagonPatterns.td46 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
123 def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>;
124 def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>;
249 def I1toI32: OutPatFrag<(ops node:$Rs), (C2_muxii (i1 $Rs), 1, 0)>;
250 def I32toI1: OutPatFrag<(ops node:$Rs), (i1 (C2_cmpgtui (i32 $Rs), (i32 0)))>;
251 def ToZext64: OutPatFrag<(ops node:$Rs), (i64 (A4_combineir 0, (i32 $Rs)))>;
252 def ToSext64: OutPatFrag<(ops node:$Rs), (i64 (A2_sxtw (i32 $Rs)))>;
253 def ToAext64: OutPatFrag<(ops node:$Rs),
254 (REG_SEQUENCE DoubleRegs, (i32 (IMPLICIT_DEF)), isub_hi, (i32 $Rs), isub_lo)>;
256 def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
[all …]
H A DHexagonPatternsHVX.td239 def: Pat<(HexagonVEXTRACTW HVI8:$Vu, I32:$Rs),
240 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
241 def: Pat<(HexagonVEXTRACTW HVI16:$Vu, I32:$Rs),
242 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
243 def: Pat<(HexagonVEXTRACTW HVI32:$Vu, I32:$Rs),
244 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
258 def V60splatrb: OutPatFrag<(ops node:$Rs), (V6_lvsplatw (S2_vsplatrb $Rs))>;
259 def V60splatrh: OutPatFrag<(ops node:$Rs),
260 (V6_lvsplatw (A2_combine_ll $Rs, $Rs))>;
261 def V60splatrw: OutPatFrag<(ops node:$Rs), (V6_lvsplatw $Rs)>;
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H A DHexagonConstExtenders.cpp291 Register Rs; member
296 ExtExpr(Register RS, bool NG, unsigned SH) : Rs(RS), S(SH), Neg(NG) {} in ExtExpr()
299 return Rs.Reg == 0; in trivial()
302 return Rs == Ex.Rs && S == Ex.S && Neg == Ex.Neg; in operator ==()
308 if (Rs != Ex.Rs) in operator <()
309 return Rs < Ex.Rs; in operator <()
444 : Rs(R), HRI(I) {} in PrintRegister()
445 HCE::Register Rs; member
451 if (P.Rs.Reg != 0) in operator <<()
452 OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); in operator <<()
[all …]
H A DHexagonIntrinsicsV5.td41 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
45 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
50 // Rdd=vpmpyh(Rs,Rt)
52 // Rxx[^]=vpmpyh(Rs,Rt)
56 // Rdd=pmpyw(Rs,Rt)
58 // Rxx^=pmpyw(Rs,Rt)
302 // Rd=[cround|round](Rs,Rt)[:sat]
303 // Rd=[cround|round](Rs,#u5)[:sat]
328 // Rdd=vmpyb[s]u(Rs,Rt)
332 // Rxx+=vmpyb[s]u(Rs,Rt)
H A DHexagonSplitDouble.cpp103 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
147 const USet &Rs = I.second; in isInduction() local
148 if (Rs.find(Reg) != Rs.end()) in isInduction()
374 Register Rs = MI->getOperand(1).getReg(); in profit() local
376 return profit(Rs) + profit(Rt); in profit()
476 USet &Rs) { in collectIndRegsForLoop() argument
560 Rs.insert(DP.begin(), End); in collectIndRegsForLoop()
561 Rs.insert(CmpR1); in collectIndRegsForLoop()
562 Rs.insert(CmpR2); in collectIndRegsForLoop()
566 dump_partition(dbgs(), Rs, *TRI); in collectIndRegsForLoop()
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H A DHexagonPseudo.td42 class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp,
51 let Inst{27} = Rs;
187 def PS_callr_nr: InstHexagon<(outs), (ins IntRegs:$Rs),
188 "callr $Rs", [], "", J2_callr.Itinerary, TypeJ>, OpcodeHexagon {
189 bits<5> Rs;
195 let Inst{20-16} = Rs;
264 (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
314 (ins IntRegs:$Rs, u32_0Imm:$A), "", []>;
333 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
426 (ins IntRegs:$Rs, s32_0Imm:$Off, HvxQR:$Qt), "", []>,
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/netbsd-src/external/gpl3/gdb/dist/cpu/
H A Dxstormy16.cpu208 (dnf f-Rs "general register source" () 8 4)
209 (dnop Rs "general register source" () h-gr f-Rs)
616 ("mov$ws2 $Rdm,($Rs)")
617 (+ OP1_7 OP2A_0 ws2 Rs OP4M_0 Rdm)
619 (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2)
620 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))
627 ("mov$ws2 $Rdm,($Rs++)")
628 (+ OP1_6 OP2A_0 ws2 Rs OP4M_0 Rdm)
631 (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2)
632 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))
[all …]
/netbsd-src/external/gpl3/binutils/dist/cpu/
H A Dxstormy16.cpu208 (dnf f-Rs "general register source" () 8 4)
209 (dnop Rs "general register source" () h-gr f-Rs)
616 ("mov$ws2 $Rdm,($Rs)")
617 (+ OP1_7 OP2A_0 ws2 Rs OP4M_0 Rdm)
619 (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2)
620 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))
627 ("mov$ws2 $Rdm,($Rs++)")
628 (+ OP1_6 OP2A_0 ws2 Rs OP4M_0 Rdm)
631 (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2)
632 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))
[all …]
H A Dcris.cpu254 ((Rs INT -1))
262 ((Rs INT -1) (Rd INT -1))
265 ((Rs INT -1) (Rd INT -1))
268 ((Rs INT -1) (Rd INT -1))
274 ((Rs INT -1))
292 ((Rd INT -1) (Rs INT -1))
299 ((Rs INT -1))
306 ((Rs INT -1))
1538 ; Rs := source operand, register addressing mode
1539 (dnop Rs "Source general register" () h-gr f-source)
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/netbsd-src/external/gpl3/binutils.old/dist/cpu/
H A Dxstormy16.cpu208 (dnf f-Rs "general register source" () 8 4)
209 (dnop Rs "general register source" () h-gr f-Rs)
616 ("mov$ws2 $Rdm,($Rs)")
617 (+ OP1_7 OP2A_0 ws2 Rs OP4M_0 Rdm)
619 (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2)
620 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))
627 ("mov$ws2 $Rdm,($Rs++)")
628 (+ OP1_6 OP2A_0 ws2 Rs OP4M_0 Rdm)
631 (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2)
632 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))
[all …]
H A Dcris.cpu254 ((Rs INT -1))
262 ((Rs INT -1) (Rd INT -1))
265 ((Rs INT -1) (Rd INT -1))
268 ((Rs INT -1) (Rd INT -1))
274 ((Rs INT -1))
292 ((Rd INT -1) (Rs INT -1))
299 ((Rs INT -1))
306 ((Rs INT -1))
1537 ; Rs := source operand, register addressing mode
1538 (dnop Rs "Source general register" () h-gr f-source)
[all …]
/netbsd-src/external/gpl3/gdb.old/dist/cpu/
H A Dxstormy16.cpu208 (dnf f-Rs "general register source" () 8 4)
209 (dnop Rs "general register source" () h-gr f-Rs)
616 ("mov$ws2 $Rdm,($Rs)")
617 (+ OP1_7 OP2A_0 ws2 Rs OP4M_0 Rdm)
619 (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2)
620 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))
627 ("mov$ws2 $Rdm,($Rs++)")
628 (+ OP1_6 OP2A_0 ws2 Rs OP4M_0 Rdm)
631 (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2)
632 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))
[all …]
H A Dcris.cpu254 ((Rs INT -1))
262 ((Rs INT -1) (Rd INT -1))
265 ((Rs INT -1) (Rd INT -1))
268 ((Rs INT -1) (Rd INT -1))
274 ((Rs INT -1))
292 ((Rd INT -1) (Rs INT -1))
299 ((Rs INT -1))
306 ((Rs INT -1))
1537 ; Rs := source operand, register addressing mode
1538 (dnop Rs "Source general register" () h-gr f-source)
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp201 MCOperand Rs, Rt; in getCompoundInsn() local
223 Rs = L.getOperand(1); in getCompoundInsn()
229 CompoundInsn->addOperand(Rs); in getCompoundInsn()
236 Rs = L.getOperand(1); in getCompoundInsn()
242 CompoundInsn->addOperand(Rs); in getCompoundInsn()
249 Rs = L.getOperand(1); in getCompoundInsn()
255 CompoundInsn->addOperand(Rs); in getCompoundInsn()
262 Rs = L.getOperand(1); in getCompoundInsn()
268 CompoundInsn->addOperand(Rs); in getCompoundInsn()
283 Rs = L.getOperand(1); in getCompoundInsn()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp636 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeDAHIDATIMMR6() local
639 Rs))); in DecodeDAHIDATIMMR6()
641 Rs))); in DecodeDAHIDATIMMR6()
650 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDAHIDATI() local
653 Rs))); in DecodeDAHIDATI()
655 Rs))); in DecodeDAHIDATI()
675 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
680 if (Rs >= Rt) { in DecodeAddiGroupBranch()
683 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
691 Rs))); in DecodeAddiGroupBranch()
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/netbsd-src/external/gpl3/gcc.old/dist/libphobos/src/std/algorithm/
H A Dsetops.d1125 struct SetIntersection(alias less = "a < b", Rs...)
1126 if (Rs.length >= 2 && allSatisfy!(isInputRange, Rs) &&
1127 !is(CommonType!(staticMap!(ElementType, Rs)) == void))
1130 Rs _input;
1132 alias ElementType = CommonType!(staticMap!(.ElementType, Rs));
1139 size_t done = Rs.length; in adjustPosition()
1140 static if (Rs.length > 1) while (true) in adjustPosition()
1144 alias next = _input[(i + 1) % Rs.length]; in adjustPosition()
1153 done = Rs.length; in adjustPosition()
1162 this(Rs input) in this()
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/netbsd-src/external/gpl3/gcc/dist/libphobos/src/std/algorithm/
H A Dsetops.d1176 struct SetIntersection(alias less = "a < b", Rs...)
1177 if (Rs.length >= 2 && allSatisfy!(isInputRange, Rs) &&
1178 !is(CommonType!(staticMap!(ElementType, Rs)) == void))
1181 Rs _input;
1183 alias ElementType = CommonType!(staticMap!(.ElementType, Rs));
1190 size_t done = Rs.length;
1191 static if (Rs.length > 1) while (true)
1195 alias next = _input[(i + 1) % Rs.length];
1204 done = Rs.length;
1213 this(Rs input)
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/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Daarch64-tbl.h3948 …CORE_INSN ("stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC,…
3949 …CORE_INSN ("stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC…
3954 …CORE_INSN ("stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC…
3955 …CORE_INSN ("stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EX…
3960 …CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC,…
3961 …CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC…
3962 …CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST…
3963 …CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDS…
4010 …_LS64_INSN ("st64bv", 0xf820b000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NI…
4011 …_LS64_INSN ("st64bv0", 0xf820a000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NI…
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Daarch64-tbl.h3740 …CORE_INSN ("stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC,…
3741 …CORE_INSN ("stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC…
3746 …CORE_INSN ("stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC…
3747 …CORE_INSN ("stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EX…
3752 …CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC,…
3753 …CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC…
3754 …CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST…
3755 …CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDS…
3802 …_LS64_INSN ("st64bv", 0xf820b000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NI…
3803 …_LS64_INSN ("st64bv0", 0xf820a000, 0xffe0fc00, lse_atomic, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NI…
[all …]
/netbsd-src/sys/external/bsd/compiler_rt/dist/lib/xray/
H A Dxray_mips.cc41 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction() argument
44 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
H A Dxray_mips64.cc42 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction() argument
45 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
49 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
51 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode() argument
155 switch (Rs) { in DecodeSrcAddrMode()
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI() local
184 return DecodeSrcAddrMode(Rs, As); in DecodeSrcAddrModeI()
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII() local
190 return DecodeSrcAddrMode(Rs, As); in DecodeSrcAddrModeII()
/netbsd-src/sys/arch/sh3/include/
H A Dlocore.h209 #define __INTR_MASK_EXCEPTION_UNBLOCK(Rs, Ri, Rb) \ argument
214 stc sr, Rs ;\
216 or Ri, Rs /* SR |= PSL_IMASK */ ;\
217 and Rb, Rs /* SR &= ~PSL_BL */ ;\
218 ldc Rs, sr
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DScalarEvolutionDivision.cpp149 SmallVector<const SCEV *, 2> Qs, Rs; in visitAddExpr() local
161 Rs.push_back(R); in visitAddExpr()
166 Remainder = Rs[0]; in visitAddExpr()
171 Remainder = SE.getAddExpr(Rs); in visitAddExpr()

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