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Searched refs:Rm (Results 1 – 25 of 117) sorted by relevance

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/netbsd-src/external/gpl3/binutils/dist/gas/doc/
H A Dc-sh.texi263 Rm @r{another numbered register}
270 add Rm,Rn mac.w @@Rm+,@@Rn+
271 addc Rm,Rn mov #imm,Rn
272 addv Rm,Rn mov Rm,Rn
273 and #imm,R0 mov.b Rm,@@(R0,Rn)
274 and Rm,Rn mov.b Rm,@@-Rn
275 and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
276 bf disp8 mov.b @@(disp,Rm),R0
278 bsr disp12 mov.b @@(R0,Rm),Rn
279 bt disp8 mov.b @@Rm+,Rn
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/gas/doc/
H A Dc-sh.texi263 Rm @r{another numbered register}
270 add Rm,Rn mac.w @@Rm+,@@Rn+
271 addc Rm,Rn mov #imm,Rn
272 addv Rm,Rn mov Rm,Rn
273 and #imm,R0 mov.b Rm,@@(R0,Rn)
274 and Rm,Rn mov.b Rm,@@-Rn
275 and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
276 bf disp8 mov.b @@(disp,Rm),R0
278 bsr disp12 mov.b @@(R0,Rm),Rn
279 bt disp8 mov.b @@Rm+,Rn
[all …]
/netbsd-src/sys/arch/aarch64/aarch64/
H A Ddisasm.c798 uint64_t sf, uint64_t Rm, uint64_t option, uint64_t imm3, in extendreg_common() argument
810 PRINTF("%s, %s", SREGNAME(sf, Rn), ZREGNAME(r, Rm)); in extendreg_common()
841 uint64_t sf, uint64_t shift, uint64_t Rm, uint64_t imm6, in shiftreg_common() argument
854 ZREGNAME(sf, Rm)); in shiftreg_common()
859 ZREGNAME(sf, Rm)); in shiftreg_common()
865 ZREGNAME(sf, Rm)); in shiftreg_common()
889 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, in regoffset_b_common() argument
904 ZREGNAME(r, Rm), in regoffset_b_common()
912 ZREGNAME(r, Rm), in regoffset_b_common()
921 uint64_t Rm, uint64_t option, uint64_t shift, uint64_t Rn, uint64_t Rt, in regoffset_h_common() argument
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrThumb.td395 let Inst{6-3} = 0b1111; // Rm = pc
454 // ADD <Rm>, sp
466 // ADD sp, <Rm>
467 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
468 "add", "\t$Rdn, $Rm", []>,
471 bits<4> Rm;
473 let Inst{6-3} = Rm;
484 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
487 bits<4> Rm;
488 let Inst{6-3} = Rm;
[all …]
H A DARMInstrThumb2.td359 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
365 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
524 bits<4> Rm;
527 let Inst{3-0} = Rm;
534 bits<4> Rm;
537 let Inst{3-0} = Rm;
544 bits<4> Rm;
547 let Inst{3-0} = Rm;
583 bits<4> Rm;
587 let Inst{3-0} = Rm;
[all …]
H A DARMInstrInfo.td1531 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1532 iir, opc, "\t$Rd, $Rn, $Rm",
1533 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1537 bits<4> Rm;
1543 let Inst{3-0} = Rm;
1604 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1605 iir, opc, "\t$Rd, $Rn, $Rm",
1610 bits<4> Rm;
1613 let Inst{3-0} = Rm;
1666 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
[all …]
H A DARMInstrNEON.td603 let Rm = 0b1111;
611 let Rm = 0b1111;
632 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
637 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
638 "vld1", Dt, "$Vd, $Rn, $Rm",
649 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
654 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
655 "vld1", Dt, "$Vd, $Rn, $Rm",
676 let Rm = 0b1111;
685 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
[all …]
H A DARMInstrCDE.td85 dag Rm;
150 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm, $imm"),
155 bits<4> Rm;
160 let Inst{15-12} = Rm{3-0};
171 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);
179 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);
190 let Iops3 = !con(IOpsPrefix, ops.Rn, ops.Rm);
476 let Rm = (ins regclass:$Vm);
484 let Rm = (ins regclass:$Qm);
498 let Iops2 = !con(IOpsPrefix, ops.Rm);
[all …]
/netbsd-src/sys/arch/sh3/include/
H A Dlocore.h169 #define __EXCEPTION_BLOCK(Rn, Rm) ;\ argument
173 stc sr, Rm ;\
174 or Rm, Rn ;\
177 #define __EXCEPTION_UNBLOCK(Rn, Rm) ;\ argument
181 stc sr, Rm ;\
182 and Rn, Rm ;\
183 ldc Rm, sr /* unblock exceptions */
189 #define __INTR_MASK(Rn, Rm) ;\ argument
192 stc sr, Rm ;\
193 or Rn, Rm ;\
[all …]
/netbsd-src/external/gpl3/gdb/dist/sim/mn10300/
H A Dam33-2.igen3 // 1111 1001 1010 0110 Rm.. 0000; dcpf (Rm)
26 // 1111 1011 1010 0110 Ri.. Rm.. 0000 0000; dcpf (Ri,Rm)
41 // 1111 1011 1010 0111 Rm.. 0000 IMM8; dcpf (d8,Rm)
55 // 1111 1101 1010 0111 Rm.. 0000 IMM24; dcpf (d24,Rm)
70 // 1111 1110 0100 0110 Rm.. 0000 IMM32; dcpf (d32,Rm)
132 // 1111 1001 0010 000X Rm.. Sn..; fmov (Rm),FSn
133 8.0xf9+4.2,3.0,1.X+4.Rm,4.Sn:D1a:::fmov
143 int reg = translate_rreg (SD_, Rm);
148 // 1111 1001 0010 001X Rm.. Sn..; fmov (Rm+),FSn
149 8.0xf9+4.2,3.1,1.X+4.Rm,4.Sn:D1b:::fmov
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrAtomics.td47 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
49 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
50 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
52 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
62 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
64 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
65 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
67 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
77 def : Pat<(relaxed_load<atomic_load_32> (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
79 (LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
[all …]
H A DAArch64InstrFormats.td1670 : AuthBase<M, (outs), (ins GPR64:$Rn, GPR64sp:$Rm), asm, "\t$Rn, $Rm", []> {
1672 bits<5> Rm;
1676 let Inst{4-0} = Rm;
1986 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64sp:$Rm),
1987 asm, "\t$Rd, $Rn, $Rm", "",
1988 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
1992 bits<5> Rm;
1994 let Inst{20-16} = Rm;
2040 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
2041 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
[all …]
H A DAArch64InstrInfo.td871 (v4bf16 V64:$Rm),
875 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
899 (AArch64duplane32 (v4i32 V128:$Rm),
1032 def : Pat<(v4f16 (int_aarch64_neon_vcadd_rot90 (v4f16 V64:$Rn), (v4f16 V64:$Rm))),
1033 (FCADDv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm), (i32 0))>;
1034 def : Pat<(v4f16 (int_aarch64_neon_vcadd_rot270 (v4f16 V64:$Rn), (v4f16 V64:$Rm))),
1035 (FCADDv4f16 (v4f16 V64:$Rn), (v4f16 V64:$Rm), (i32 1))>;
1036 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot90 (v8f16 V128:$Rn), (v8f16 V128:$Rm))),
1037 (FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 0))>;
1038 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot270 (v8f16 V128:$Rn), (v8f16 V128:$Rm))),
[all …]
H A DAArch64SchedA64FX.td2520 // [76] "ctermeq $Rn, $Rm";
2523 // [77] "ctermne $Rn, $Rm";
2858 // [189] "index $Zd, $Rn, $Rm";
2864 // [191] "index $Zd, $imm5, $Rm";
2870 // [193] "insr $Zdn, $Rm";
2888 // [199] "ld1b $Zt, $Pg/z, [$Rn, $Rm]";
2900 // [203] "ld1d $Zt, $Pg/z, [$Rn, $Rm]";
2912 // [207] "ld1h $Zt, $Pg/z, [$Rn, $Rm]";
2933 // [214] "ld1rqb $Zt, $Pg/z, [$Rn, $Rm]";
2939 // [216] "ld1rqd $Zt, $Pg/z, [$Rn, $Rm]";
[all …]
H A DSVEInstrFormats.td1289 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm),
1290 asm, "\t$Zdn, $Rm",
1293 bits<5> Rm;
1298 let Inst{9-5} = Rm;
4531 : I<(outs), (ins rt:$Rn, rt:$Rm),
4532 asm, "\t$Rn, $Rm",
4535 bits<5> Rm;
4540 let Inst{20-16} = Rm;
4551 : I<(outs pprty:$Pd), (ins gprty:$Rn, gprty:$Rm),
4552 asm, "\t$Pd, $Rn, $Rm",
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1474 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegImmOperand() local
1479 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegImmOperand()
1511 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegRegOperand() local
1516 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegRegOperand()
1850 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode2IdxInstruction() local
1912 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1954 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegMemOperand() local
1980 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegMemOperand()
1999 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode3Instruction() local
2032 if (type && Rm == 15) in DecodeAddrMode3Instruction()
[all …]
/netbsd-src/external/gpl3/binutils/dist/cpu/
H A Dmep-fmax.cpu179 (dnop fmax-Rm "Rm" (all-fmax-isas) h-gpr f-fmax-rm)
302 "cmov FRn,Rm"
304 "cmov ${fmax-FRd-int},${fmax-Rm}"
305 (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
308 (set fmax-FRd-int fmax-Rm)
312 "cmov Rm,FRn"
314 "cmov ${fmax-Rm},${fmax-FRd-int}"
315 (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
318 (set fmax-Rm fmax-FRd-int)
322 "cmovc CCRn,Rm"
[all …]
H A Dxstormy16.cpu205 (dnf f-Rm "general register for memory" () 4 3)
206 (dnop Rm "general register for memory" () h-gr f-Rm)
574 ("mov$ws2 $Rm,$lmem8")
575 (+ OP1_8 Rm ws2 lmem8)
577 (set-psw Rm (index-of Rm) (alignfix-mem lmem8) ws2)
578 (set-psw Rm (index-of Rm) (mem QI lmem8) ws2))
584 ("mov$ws2 $Rm,$hmem8")
585 (+ OP1_A Rm ws2 hmem8)
587 (set-psw Rm (index-of Rm) (alignfix-mem hmem8) ws2)
588 (set-psw Rm (index-of Rm) (mem QI hmem8) ws2))
[all …]
/netbsd-src/external/gpl3/gdb.old/dist/cpu/
H A Dmep-fmax.cpu179 (dnop fmax-Rm "Rm" (all-fmax-isas) h-gpr f-fmax-rm)
302 "cmov FRn,Rm"
304 "cmov ${fmax-FRd-int},${fmax-Rm}"
305 (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
308 (set fmax-FRd-int fmax-Rm)
312 "cmov Rm,FRn"
314 "cmov ${fmax-Rm},${fmax-FRd-int}"
315 (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
318 (set fmax-Rm fmax-FRd-int)
322 "cmovc CCRn,Rm"
[all …]
H A Dxstormy16.cpu205 (dnf f-Rm "general register for memory" () 4 3)
206 (dnop Rm "general register for memory" () h-gr f-Rm)
574 ("mov$ws2 $Rm,$lmem8")
575 (+ OP1_8 Rm ws2 lmem8)
577 (set-psw Rm (index-of Rm) (alignfix-mem lmem8) ws2)
578 (set-psw Rm (index-of Rm) (mem QI lmem8) ws2))
584 ("mov$ws2 $Rm,$hmem8")
585 (+ OP1_A Rm ws2 hmem8)
587 (set-psw Rm (index-of Rm) (alignfix-mem hmem8) ws2)
588 (set-psw Rm (index-of Rm) (mem QI hmem8) ws2))
[all …]
/netbsd-src/external/gpl3/gdb/dist/cpu/
H A Dmep-fmax.cpu179 (dnop fmax-Rm "Rm" (all-fmax-isas) h-gpr f-fmax-rm)
302 "cmov FRn,Rm"
304 "cmov ${fmax-FRd-int},${fmax-Rm}"
305 (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
308 (set fmax-FRd-int fmax-Rm)
312 "cmov Rm,FRn"
314 "cmov ${fmax-Rm},${fmax-FRd-int}"
315 (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
318 (set fmax-Rm fmax-FRd-int)
322 "cmovc CCRn,Rm"
[all …]
H A Dxstormy16.cpu205 (dnf f-Rm "general register for memory" () 4 3)
206 (dnop Rm "general register for memory" () h-gr f-Rm)
574 ("mov$ws2 $Rm,$lmem8")
575 (+ OP1_8 Rm ws2 lmem8)
577 (set-psw Rm (index-of Rm) (alignfix-mem lmem8) ws2)
578 (set-psw Rm (index-of Rm) (mem QI lmem8) ws2))
584 ("mov$ws2 $Rm,$hmem8")
585 (+ OP1_A Rm ws2 hmem8)
587 (set-psw Rm (index-of Rm) (alignfix-mem hmem8) ws2)
588 (set-psw Rm (index-of Rm) (mem QI hmem8) ws2))
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/cpu/
H A Dmep-fmax.cpu179 (dnop fmax-Rm "Rm" (all-fmax-isas) h-gpr f-fmax-rm)
302 "cmov FRn,Rm"
304 "cmov ${fmax-FRd-int},${fmax-Rm}"
305 (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
308 (set fmax-FRd-int fmax-Rm)
312 "cmov Rm,FRn"
314 "cmov ${fmax-Rm},${fmax-FRd-int}"
315 (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
318 (set fmax-Rm fmax-FRd-int)
322 "cmovc CCRn,Rm"
[all …]
H A Dxstormy16.cpu205 (dnf f-Rm "general register for memory" () 4 3)
206 (dnop Rm "general register for memory" () h-gr f-Rm)
574 ("mov$ws2 $Rm,$lmem8")
575 (+ OP1_8 Rm ws2 lmem8)
577 (set-psw Rm (index-of Rm) (alignfix-mem lmem8) ws2)
578 (set-psw Rm (index-of Rm) (mem QI lmem8) ws2))
584 ("mov$ws2 $Rm,$hmem8")
585 (+ OP1_A Rm ws2 hmem8)
587 (set-psw Rm (index-of Rm) (alignfix-mem hmem8) ws2)
588 (set-psw Rm (index-of Rm) (mem QI hmem8) ws2))
[all …]
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Daarch64-tbl.h2921 OP3 (MOPS_ADDR_Rd, MOPS_WB_Rn, Rm), QL_I3SAMEX, FLAGS, \
2949 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
2950 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
2951 …CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_AL…
2952 …CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS …
2953 …CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_AL…
2954 …CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS …
3643 …CORE_INSN ("ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg, 0, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF…
3644 …CORE_INSN ("ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg, 0, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF…
3646 CORE_INSN ("csel", 0x1a800000, 0x7fe00c00, condsel, 0, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF),
[all …]

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