| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.cpp | 24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
27 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
41 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
197 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
200 RegList = RRegList; in CC_ARM_AAPCS_Custom_Aggregate()
201 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate()
206 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
207 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
214 RegList = SRegList; in CC_ARM_AAPCS_Custom_Aggregate()
219 RegList = DRegList; in CC_ARM_AAPCS_Custom_Aggregate()
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| H A D | Thumb2ITBlockPass.cpp | 83 using RegList = SmallVector<unsigned, 4>; in INITIALIZE_PASS() typedef
84 RegList LocalDefs; in INITIALIZE_PASS()
85 RegList LocalUses; in INITIALIZE_PASS()
99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { in INITIALIZE_PASS()
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| H A D | ARMAsmPrinter.cpp | 1125 SmallVector<unsigned, 4> RegList; in EmitUnwindingInstruction() local
1158 assert(RegList.empty() && in EmitUnwindingInstruction()
1170 RegList.push_back(Reg); in EmitUnwindingInstruction()
1178 RegList.push_back(SrcReg); in EmitUnwindingInstruction()
1182 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); in EmitUnwindingInstruction()
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| H A D | ARMBaseRegisterInfo.cpp | 70 const MCPhysReg *RegList = in getCalleeSavedRegs() local
111 return RegList; in getCalleeSavedRegs()
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| H A D | ARMBaseInstrInfo.cpp | 2543 SmallVector<MachineOperand, 4> RegList; in tryFoldSPUpdateIntoPushPop() local
2552 RegList.push_back(MO); in tryFoldSPUpdateIntoPushPop()
2571 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, in tryFoldSPUpdateIntoPushPop()
2593 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false, in tryFoldSPUpdateIntoPushPop()
2609 for (int i = RegList.size() - 1; i >= 0; --i) in tryFoldSPUpdateIntoPushPop()
2610 MIB.add(RegList[i]); in tryFoldSPUpdateIntoPushPop()
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| H A D | ARMInstrInfo.td | 578 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CallingConvEmitter.cpp | 126 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
127 if (RegList->size() == 1) { in EmitAction()
129 O << getQualifiedName(RegList->getElementAsRecord(0)) << ")) {\n"; in EmitAction()
135 for (unsigned i = 0, e = RegList->size(); i != e; ++i) in EmitAction()
136 O << LS << getQualifiedName(RegList->getElementAsRecord(i)); in EmitAction()
146 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
148 if (!ShadowRegList->empty() && ShadowRegList->size() != RegList->size()) in EmitAction()
152 if (RegList->size() == 1) { in EmitAction()
154 O << getQualifiedName(RegList->getElementAsRecord(0)); in EmitAction()
165 for (unsigned i = 0, e = RegList->size(); i != e; ++i) in EmitAction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.cpp | 132 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block() local
134 RegList = XRegList; in CC_AArch64_Custom_Block()
136 RegList = HRegList; in CC_AArch64_Custom_Block()
138 RegList = SRegList; in CC_AArch64_Custom_Block()
140 RegList = DRegList; in CC_AArch64_Custom_Block()
142 RegList = QRegList; in CC_AArch64_Custom_Block()
144 RegList = ZRegList; in CC_AArch64_Custom_Block()
164 RegList, alignTo(PendingMembers.size(), EltsPerReg) / EltsPerReg); in CC_AArch64_Custom_Block()
191 for (auto Reg : RegList) in CC_AArch64_Custom_Block()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86CallingConv.cpp | 33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs() local
40 for (auto Reg : RegList) { in CC_X86_32_RegCall_Assign2Regs()
96 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister() local
101 for (auto Reg : RegList) { in CC_X86_VectorCallAssignRegister()
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg() local
243 static const unsigned NumRegs = sizeof(RegList) / sizeof(RegList[0]); in CC_X86_32_MCUInReg()
261 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
277 unsigned FirstFree = State.getFirstUnallocated(RegList); in CC_X86_32_MCUInReg()
282 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMELFStreamer.cpp | 85 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
157 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
159 assert(RegList.size() && "RegList should not be empty"); in emitRegSave()
165 InstPrinter.printRegName(OS, RegList[0]); in emitRegSave()
167 for (unsigned i = 1, e = RegList.size(); i != e; ++i) { in emitRegSave()
169 InstPrinter.printRegName(OS, RegList[i]); in emitRegSave()
389 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
459 void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
761 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
763 getStreamer().emitRegSave(RegList, isVector); in emitRegSave()
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| H A D | ARMTargetStreamer.cpp | 98 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetCallingConv.td | 113 list<Register> RegList = regList;
120 list<Register> RegList = regList;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 468 ArrayRef<MCPhysReg> RegList; in AnalyzeArguments() local
473 RegList = BuiltinRegList; in AnalyzeArguments()
476 RegList = CRegList; in AnalyzeArguments()
529 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
537 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 58 static const MCPhysReg RegList[] = { in CC_Sparc_Assign_Split_64() local
62 if (Register Reg = State.AllocateReg(RegList)) { in CC_Sparc_Assign_Split_64()
72 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Split_64()
84 static const MCPhysReg RegList[] = { in CC_Sparc_Assign_Ret_Split_64() local
89 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
95 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCStreamer.h | 146 virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 839 delete RegList.List; in ~MipsOperand()
882 struct RegListOp RegList; member
1412 int Size = RegList.List->size(); in isRegList16()
1416 unsigned R0 = RegList.List->front(); in isRegList16()
1417 unsigned R1 = RegList.List->back(); in isRegList16()
1422 int PrevReg = *RegList.List->begin(); in isRegList16()
1424 int Reg = (*(RegList.List))[i]; in isRegList16()
1488 return *(RegList.List); in getRegList()
1592 Op->RegList.List = new SmallVector<unsigned, 10>(Regs.begin(), Regs.end()); in CreateRegList()
1722 for (auto Reg : (*RegList.List)) in print()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2573 const SmallVectorImpl<unsigned> &RegList = getRegList(); in addRegListOperands() local
2575 I = RegList.begin(), E = RegList.end(); I != E; ++I) in addRegListOperands()
2581 const SmallVectorImpl<unsigned> &RegList = getRegList(); in addRegListWithAPSROperands() local
2583 I = RegList.begin(), E = RegList.end(); I != E; ++I) in addRegListWithAPSROperands()
4017 const SmallVectorImpl<unsigned> &RegList = getRegList(); in print() local
4019 I = RegList.begin(), E = RegList.end(); I != E; ) { in print()
8222 auto &RegList = Op.getRegList(); in validateInstruction() local
8223 if (RegList.size() < 1 || RegList.size() > 16) in validateInstruction()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrInfo.td | 518 let Name = "RegList";
|