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Searched refs:RW (Results 1 – 25 of 121) sorted by relevance

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/netbsd-src/sys/dev/ic/
H A Darn9285.c195 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI); in ar9285_init_from_rom()
196 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ); in ar9285_init_from_rom()
201 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, in ar9285_init_from_rom()
203 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, in ar9285_init_from_rom()
205 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, in ar9285_init_from_rom()
207 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, in ar9285_init_from_rom()
213 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, in ar9285_init_from_rom()
215 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, in ar9285_init_from_rom()
217 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, in ar9285_init_from_rom()
219 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, in ar9285_init_from_rom()
[all …]
H A Darn9287.c176 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, in ar9287_init_from_rom()
178 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, in ar9287_init_from_rom()
183 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, in ar9287_init_from_rom()
185 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, in ar9287_init_from_rom()
190 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, in ar9287_init_from_rom()
192 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, in ar9287_init_from_rom()
200 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40); in ar9287_init_from_rom()
203 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); in ar9287_init_from_rom()
207 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); in ar9287_init_from_rom()
217 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); in ar9287_init_from_rom()
[all …]
H A Darn9380.c317 reg = RW(reg, AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL, in ar9380_init_from_rom()
323 reg = RW(reg, AR_PHY_65NM_CH0_TOP_XPABIASLVL, in ar9380_init_from_rom()
327 reg = RW(reg, AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB, in ar9380_init_from_rom()
335 reg = RW(reg, AR_SWITCH_TABLE_COM_ALL, modal->antCtrlCommon); in ar9380_init_from_rom()
338 reg = RW(reg, AR_SWITCH_TABLE_COM_2_ALL, modal->antCtrlCommon2); in ar9380_init_from_rom()
344 reg = RW(reg, AR_SWITCH_TABLE_ALL, modal->antCtrlChain[i]); in ar9380_init_from_rom()
351 reg = RW(reg, AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL, in ar9380_init_from_rom()
369 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_0, 5); in ar9380_init_from_rom()
370 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_1, 5); in ar9380_init_from_rom()
371 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_2, 5); in ar9380_init_from_rom()
[all …]
H A Darn9280.c221 reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1); in ar9280_set_synth()
257 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, in ar9280_init_from_rom()
259 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, in ar9280_init_from_rom()
265 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, in ar9280_init_from_rom()
267 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, in ar9280_init_from_rom()
269 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, in ar9280_init_from_rom()
271 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, in ar9280_init_from_rom()
280 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, in ar9280_init_from_rom()
282 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, in ar9280_init_from_rom()
288 reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob); in ar9280_init_from_rom()
[all …]
H A Darn5416.c248 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, in ar5416_init_from_rom()
250 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, in ar5416_init_from_rom()
259 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_MARGIN, in ar5416_init_from_rom()
261 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_ATTEN, in ar5416_init_from_rom()
270 reg = RW(reg, AR_PHY_RXGAIN_TXRX_ATTEN, txRxAtten); in ar5416_init_from_rom()
274 reg = RW(reg, AR_PHY_GAIN_2GHZ_RXTX_MARGIN, in ar5416_init_from_rom()
279 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); in ar5416_init_from_rom()
283 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); in ar5416_init_from_rom()
284 reg = RW(reg, AR_PHY_DESIRED_SZ_PGA, modal->pgaDesiredSize); in ar5416_init_from_rom()
294 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn); in ar5416_init_from_rom()
[all …]
H A Darn9003.c588 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); in ar9003_rfsilent_init()
844 reg = RW(reg, AR_RXBP_THRESH_HP, 1); in ar9003_rx_enable()
845 reg = RW(reg, AR_RXBP_THRESH_LP, 1); in ar9003_rx_enable()
1953 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); in ar9003_set_delta_slope()
1954 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); in ar9003_set_delta_slope()
1963 reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp); in ar9003_set_delta_slope()
1964 reg = RW(reg, AR_PHY_SGI_DSC_MAN, man); in ar9003_set_delta_slope()
2059 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); in ar9003_write_noisefloor()
2063 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]); in ar9003_write_noisefloor()
2218 reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 10); in ar9003_do_calib()
[all …]
H A Darn5008.c458 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); in ar5008_rfsilent_init()
1778 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); in ar5008_set_delta_slope()
1779 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); in ar5008_set_delta_slope()
1788 reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp); in ar5008_set_delta_slope()
1789 reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man); in ar5008_set_delta_slope()
1892 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); in ar5008_write_noisefloor()
1896 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]); in ar5008_write_noisefloor()
1991 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, log); in ar5008_do_calib()
2079 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, i_coff); in ar5008_calib_iq()
2080 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, q_coff); in ar5008_calib_iq()
[all …]
/netbsd-src/sys/dev/microcode/aic7xxx/
H A Daic79xx.reg99 access_mode RW
113 access_mode RW
130 access_mode RW
256 access_mode RW
272 access_mode RW
281 access_mode RW
289 access_mode RW
325 access_mode RW
334 access_mode RW
344 access_mode RW
[all …]
H A Daic7xxx.reg59 access_mode RW
76 access_mode RW
92 access_mode RW
169 access_mode RW
185 access_mode RW
207 access_mode RW
212 access_mode RW
225 access_mode RW
231 access_mode RW
240 access_mode RW
[all …]
/netbsd-src/sys/external/bsd/compiler_rt/dist/lib/tsan/tests/rtl/
H A Dtsan_test_util_posix.cc110 else if (type_ == RW) in Init()
133 else if (type_ == RW) in Destroy()
145 else if (type_ == RW) in Lock()
157 else if (type_ == RW) in TryLock()
170 else if (type_ == RW) in Unlock()
176 CHECK(type_ == RW); in ReadLock()
182 CHECK(type_ == RW); in TryReadLock()
188 CHECK(type_ == RW); in ReadUnlock()
H A Dtsan_mop.cc69 Mutex m(Mutex::RW); in TEST()
88 Mutex m(Mutex::RW); in TEST()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); in mask() local
101 return IsSubLo ? BT::BitMask(0, RW-1) in mask()
102 : BT::BitMask(RW, 2*RW-1); in mask()
275 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
277 assert(RW <= RC.width()); in evaluate()
278 return eXTR(RC, 0, RW); in evaluate()
281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate() argument
284 assert(RW <= W); in evaluate()
285 return eXTR(RC, W-RW, W); in evaluate()
345 uint16_t RW = W0; in evaluate() local
[all …]
/netbsd-src/usr.bin/uuencode/
H A Duuencode.c99 #define RW (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) in main() macro
100 mode = RW & ~umask(RW); in main()
/netbsd-src/external/gpl3/binutils/dist/ld/scripttempl/
H A Dalphavms.sc26 /* RW initialized data. */
30 /* RW data unmodified (zero-initialized). */
/netbsd-src/external/gpl3/binutils.old/dist/ld/scripttempl/
H A Dalphavms.sc26 /* RW initialized data. */
30 /* RW data unmodified (zero-initialized). */
/netbsd-src/external/cddl/dtracetoolkit/dist/Examples/
H A Dfsrw_example.txt7 Event Device RW Size Offset Path
44 Event Device RW Size Offset Path
81 Event Device RW Size Offset Path
106 Event Device RW Size Offset Path
H A Ddiskhits_example.txt48 Total RW: 46064 KB
96 Total RW: 29392 KB
/netbsd-src/external/cddl/dtracetoolkit/dist/Docs/Examples/
H A Dfsrw_example.txt7 Event Device RW Size Offset Path
44 Event Device RW Size Offset Path
81 Event Device RW Size Offset Path
106 Event Device RW Size Offset Path
H A Ddiskhits_example.txt48 Total RW: 46064 KB
96 Total RW: 29392 KB
/netbsd-src/external/gpl2/groff/dist/contrib/mom/examples/
H A Dtypesetting.mom93 .RW .1 \" Reduce Whitespace between letters to tighten this line
95 .RW 0 \" Back to normal spacing between letters
157 .RW .04 \" Kern the whole next line slightly, so "lipstick" doesn't hyphenate.
160 .RW 0 \" Reset kerning to 0
248 .BR_AT_LINE_KERN \" Automatically insert a line break (.BR) with each invocation of .RW and .EW
270 .RW .1
273 .RW 0 \" Restore normal kerning
552 \f[HB]\*S[-1]Line "tightened" \(en .RW .1\*S[+1]\*[PREV]
553 .RW .1
558 \# (Helvetica instead of Palatino), the RW macro doesn't affect it.
[all …]
/netbsd-src/external/apache2/llvm/dist/clang/utils/ABITest/
H A DEnumeration.py152 LW,RW = W//2, W - (W//2)
153 L,R = getNthPairBounded(N, H**LW, H**RW)
155 getNthNTuple(R,RW,H=H,useLeftToRight=useLeftToRight))
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp601 for (Record *RW : RWs) { in collectSchedRW()
602 if (RW->isSubClassOf("SchedWrite")) in collectSchedRW()
603 scanSchedRW(RW, SWDefs, RWSet); in collectSchedRW()
605 assert(RW->isSubClassOf("SchedRead") && "Unknown SchedReadWrite"); in collectSchedRW()
606 scanSchedRW(RW, SRDefs, RWSet); in collectSchedRW()
681 CodeGenSchedRW &RW = getSchedRW(MatchDef); in collectSchedRW() local
682 if (RW.IsAlias) in collectSchedRW()
684 RW.Aliases.push_back(ADef); in collectSchedRW()
724 RWVec, [Def](const CodeGenSchedRW &RW) { return RW.TheDef == Def; }); in getSchedRWIdx() argument
834 auto I = find_if(RWVec, [Seq](CodeGenSchedRW &RW) { in findRWForSequence() argument
[all …]
/netbsd-src/sys/dev/pci/
H A Dif_rtwn.c850 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | in rtwn_rf_read()
891 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); in rtwn_efuse_read_1()
1168 reg = RW(reg, R92C_CR_NETTYPE, type); in rtwn_set_nettype0_msr()
1379 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); in rtwn_newstate()
1383 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); in rtwn_newstate()
1417 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); in rtwn_newstate()
1419 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); in rtwn_newstate()
1425 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); in rtwn_newstate()
1427 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); in rtwn_newstate()
2433 reg = RW(reg, R92C_MCUFWDL_PAGE, page); in rtwn_fw_loadpage()
[all …]
/netbsd-src/external/gpl3/gcc/dist/libgcc/config/rs6000/
H A Dcrtdbase.S28 .csect __gcc_unwind_dbase[RW],2
/netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/rs6000/
H A Dcrtdbase.S28 .csect __gcc_unwind_dbase[RW],2

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