195 	reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI);  in ar9285_init_from_rom()
196 	reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ);  in ar9285_init_from_rom()
201 		reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,  in ar9285_init_from_rom()
203 		reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,  in ar9285_init_from_rom()
205 		reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,  in ar9285_init_from_rom()
207 		reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,  in ar9285_init_from_rom()
213 		reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,  in ar9285_init_from_rom()
215 		reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,  in ar9285_init_from_rom()
217 		reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,  in ar9285_init_from_rom()
219 		reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,  in ar9285_init_from_rom()
228 	reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);  in ar9285_init_from_rom()
229 	reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);  in ar9285_init_from_rom()
234 	reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);  in ar9285_init_from_rom()
235 	reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);  in ar9285_init_from_rom()
241 		reg = RW(reg, AR9285_PHY_ANT_DIV_CTL_ALL, 0);  in ar9285_init_from_rom()
242 		reg = RW(reg, AR9285_PHY_ANT_DIV_CTL,  in ar9285_init_from_rom()
244 		reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_LNACONF,  in ar9285_init_from_rom()
246 		reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_LNACONF,  in ar9285_init_from_rom()
248 		reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_GAINTB,  in ar9285_init_from_rom()
250 		reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_GAINTB,  in ar9285_init_from_rom()
314 		reg = RW(reg, AR9271_AN_RF2G3_OB_CCK, ob [0]);  in ar9285_init_from_rom()
315 		reg = RW(reg, AR9271_AN_RF2G3_OB_PSK, ob [1]);  in ar9285_init_from_rom()
316 		reg = RW(reg, AR9271_AN_RF2G3_OB_QAM, ob [2]);  in ar9285_init_from_rom()
317 		reg = RW(reg, AR9271_AN_RF2G3_DB1,    db1[0]);  in ar9285_init_from_rom()
322 		reg = RW(reg, AR9271_AN_RF2G4_DB2, (uint32_t)db2[0]);  in ar9285_init_from_rom()
331 		reg = RW(reg, AR9285_AN_RF2G3_OB_0,  ob [0]);  in ar9285_init_from_rom()
332 		reg = RW(reg, AR9285_AN_RF2G3_OB_1,  ob [1]);  in ar9285_init_from_rom()
333 		reg = RW(reg, AR9285_AN_RF2G3_OB_2,  ob [2]);  in ar9285_init_from_rom()
334 		reg = RW(reg, AR9285_AN_RF2G3_OB_3,  ob [3]);  in ar9285_init_from_rom()
335 		reg = RW(reg, AR9285_AN_RF2G3_OB_4,  ob [4]);  in ar9285_init_from_rom()
336 		reg = RW(reg, AR9285_AN_RF2G3_DB1_0, db1[0]);  in ar9285_init_from_rom()
337 		reg = RW(reg, AR9285_AN_RF2G3_DB1_1, db1[1]);  in ar9285_init_from_rom()
338 		reg = RW(reg, AR9285_AN_RF2G3_DB1_2, db1[2]);  in ar9285_init_from_rom()
343 		reg = RW(reg, AR9285_AN_RF2G4_DB1_3, db1[3]);  in ar9285_init_from_rom()
344 		reg = RW(reg, AR9285_AN_RF2G4_DB1_4, db1[4]);  in ar9285_init_from_rom()
345 		reg = RW(reg, AR9285_AN_RF2G4_DB2_0, db2[0]);  in ar9285_init_from_rom()
346 		reg = RW(reg, AR9285_AN_RF2G4_DB2_1, db2[1]);  in ar9285_init_from_rom()
347 		reg = RW(reg, AR9285_AN_RF2G4_DB2_2, db2[2]);  in ar9285_init_from_rom()
348 		reg = RW(reg, AR9285_AN_RF2G4_DB2_3, db2[3]);  in ar9285_init_from_rom()
349 		reg = RW(reg, AR9285_AN_RF2G4_DB2_4, db2[4]);  in ar9285_init_from_rom()
356 	reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);  in ar9285_init_from_rom()
360 	reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);  in ar9285_init_from_rom()
370 	reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);  in ar9285_init_from_rom()
374 	reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);  in ar9285_init_from_rom()
378 	reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);  in ar9285_init_from_rom()
383 		reg = RW(reg, AR_PHY_TX_END_PA_ON,  in ar9285_init_from_rom()
385 		reg = RW(reg, AR_PHY_TX_END_DATA_START,  in ar9285_init_from_rom()
392 		reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);  in ar9285_init_from_rom()
441 	reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);  in ar9285_pa_calib()
445 	reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);  in ar9285_pa_calib()
452 	reg = RW(reg, AR9285_AN_RF2G6_CCOMP, 0xf);  in ar9285_pa_calib()
497 	reg = RW(reg, AR9285_AN_RF2G6_CCOMP, ccomp_svg);  in ar9285_pa_calib()
539 	reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);  in ar9271_pa_calib()
543 	reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);  in ar9271_pa_calib()
549 	reg = RW(reg, AR9271_AN_RF2G3_CCOMP, 0xfff);  in ar9271_pa_calib()
695 		reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x5);  in ar9285_init_calib()
697 		reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x4);  in ar9285_init_calib()
764 	reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);  in ar9285_set_power_calib()
765 	reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);  in ar9285_set_power_calib()
766 	reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);  in ar9285_set_power_calib()