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Searched refs:REG (Results 1 – 25 of 793) sorted by relevance

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/netbsd-src/sys/arch/sh3/sh3/
H A Ddevreg.c103 SH ## x ## REG(TRA); \
104 SH ## x ## REG(EXPEVT); \
105 SH ## x ## REG(INTEVT); \
107 SH ## x ## REG(BARA); \
108 SH ## x ## REG(BAMRA); \
109 SH ## x ## REG(BASRA); \
110 SH ## x ## REG(BBRA); \
111 SH ## x ## REG(BARB); \
112 SH ## x ## REG(BAMRB); \
113 SH ## x ## REG(BASRB); \
[all …]
/netbsd-src/external/gpl3/binutils/dist/gas/config/
H A Drx-parse.y145 %type <regno> REG FLAG CREG BCND BMCND SCCND ACC DREG DREGH DREGL DCREG DCMP
149 %token REG FLAG CREG ACC DREG DREGH DREGL DCREG
283 | MOV DOT_B '#' EXPR ',' '[' REG ']'
286 | MOV DOT_W '#' EXPR ',' '[' REG ']'
289 | MOV DOT_L '#' EXPR ',' '[' REG ']'
292 | MOV DOT_B '#' EXPR ',' disp '[' REG ']'
300 | MOV DOT_W '#' EXPR ',' disp '[' REG ']'
306 | MOV DOT_L '#' EXPR ',' disp '[' REG ']'
314 | RTSD '#' EXPR ',' REG '-' REG
323 | CMP REG ',' REG
[all …]
H A Dbfin-parse.y477 %token REG
604 %type <reg> REG
801 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
831 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
832 COLON expr COMMA REG COLON expr RPAREN aligndir
849 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
850 REG COLON expr RPAREN aligndir
867 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
881 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
894 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
[all …]
H A Dbfin-lex.l47 [sS][fF][tT][rR][eE][sS][eE][tT] _REG.regno = REG_sftreset; return REG;
48 [oO][mM][oO][dD][eE] _REG.regno = REG_omode; return REG;
49 [iI][dD][lL][eE]_[rR][eE][qQ] _REG.regno = REG_idle_req; return REG;
50 [hH][wW][eE][rR][rR][cC][aA][uU][sS][eE] _REG.regno = REG_hwerrcause; return REG;
51 [eE][xX][cC][aA][uU][sS][eE] _REG.regno = REG_excause; return REG;
52 [eE][mM][uU][cC][aA][uU][sS][eE] _REG.regno = REG_emucause; return REG;
59 [uU][sS][pP] _REG.regno = REG_USP; return REG;
66 [sS][yY][sS][cC][fF][gG] _REG.regno = REG_SYSCFG; return REG;
71 [sS][pP] _REG.regno = REG_SP; return REG;
74 [sS][eE][qQ][sS][tT][aA][tT] _REG.regno = REG_SEQSTAT; return REG;
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/gas/config/
H A Drx-parse.y145 %type <regno> REG FLAG CREG BCND BMCND SCCND ACC DREG DREGH DREGL DCREG DCMP
149 %token REG FLAG CREG ACC DREG DREGH DREGL DCREG
283 | MOV DOT_B '#' EXPR ',' '[' REG ']'
286 | MOV DOT_W '#' EXPR ',' '[' REG ']'
289 | MOV DOT_L '#' EXPR ',' '[' REG ']'
292 | MOV DOT_B '#' EXPR ',' disp '[' REG ']'
300 | MOV DOT_W '#' EXPR ',' disp '[' REG ']'
306 | MOV DOT_L '#' EXPR ',' disp '[' REG ']'
314 | RTSD '#' EXPR ',' REG '-' REG
323 | CMP REG ',' REG
[all …]
H A Dbfin-parse.y477 %token REG
604 %type <reg> REG
801 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
831 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
832 COLON expr COMMA REG COLON expr RPAREN aligndir
849 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
850 REG COLON expr RPAREN aligndir
867 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
881 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
894 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
[all …]
H A Dbfin-lex.l47 [sS][fF][tT][rR][eE][sS][eE][tT] _REG.regno = REG_sftreset; return REG;
48 [oO][mM][oO][dD][eE] _REG.regno = REG_omode; return REG;
49 [iI][dD][lL][eE]_[rR][eE][qQ] _REG.regno = REG_idle_req; return REG;
50 [hH][wW][eE][rR][rR][cC][aA][uU][sS][eE] _REG.regno = REG_hwerrcause; return REG;
51 [eE][xX][cC][aA][uU][sS][eE] _REG.regno = REG_excause; return REG;
52 [eE][mM][uU][cC][aA][uU][sS][eE] _REG.regno = REG_emucause; return REG;
59 [uU][sS][pP] _REG.regno = REG_USP; return REG;
66 [sS][yY][sS][cC][fF][gG] _REG.regno = REG_SYSCFG; return REG;
71 [sS][pP] _REG.regno = REG_SP; return REG;
74 [sS][eE][qQ][sS][tT][aA][tT] _REG.regno = REG_SEQSTAT; return REG;
[all …]
/netbsd-src/usr.sbin/gspa/gspa/
H A Dgsp_inst.c99 #define EXREG (REG|EXPR)
100 #define EAREG (REG|EA)
101 #define EXAREG (REG|EXPR|EA)
104 #define OPTREG (OPTOPRN|REG)
126 {"ABS", 0x0380, ONEREG, {REG, 0, 0, 0}},
127 {"ADD", 0x4000, ADD, {EXREG, REG, OPTSPEC,0}},
128 {"ADDC",0x4200, TWOREG, {REG, REG, 0, 0}},
129 {"ADDI",0x0B20, IMMREG, {EXPR, REG, OPTSPEC,0}},
130 {"ADDK",0x1000, K32REG, {EXPR, REG, 0, 0}},
131 {"ADDXY",0xE000,TWOREG, {REG, REG, 0, 0}},
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/
H A Damdgpu_hw_translate_dce120.c56 #define REG(reg_name)\ macro
74 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
104 case REG(DC_GPIO_HPD_A): in offset_to_id()
131 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
146 case REG(DC_GPIO_GENLK_A): in offset_to_id()
170 case REG(DC_GPIO_DDC1_A): in offset_to_id()
173 case REG(DC_GPIO_DDC2_A): in offset_to_id()
176 case REG(DC_GPIO_DDC3_A): in offset_to_id()
179 case REG(DC_GPIO_DDC4_A): in offset_to_id()
182 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/
H A Damdgpu_hw_translate_dcn10.c56 #define REG(reg_name)\ macro
74 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
104 case REG(DC_GPIO_HPD_A): in offset_to_id()
131 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
146 case REG(DC_GPIO_GENLK_A): in offset_to_id()
170 case REG(DC_GPIO_DDC1_A): in offset_to_id()
173 case REG(DC_GPIO_DDC2_A): in offset_to_id()
176 case REG(DC_GPIO_DDC3_A): in offset_to_id()
179 case REG(DC_GPIO_DDC4_A): in offset_to_id()
182 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_dpp_cm.c47 #define REG(reg)\ macro
130 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); in program_gamut_remap()
131 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); in program_gamut_remap()
140 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); in program_gamut_remap()
141 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); in program_gamut_remap()
150 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); in program_gamut_remap()
151 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); in program_gamut_remap()
225 gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12); in dpp1_cm_program_color_matrix()
226 gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34); in dpp1_cm_program_color_matrix()
230 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); in dpp1_cm_program_color_matrix()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/
H A Damdgpu_hw_translate_dcn20.c59 #undef REG
60 #define REG(reg_name)\ macro
78 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
108 case REG(DC_GPIO_HPD_A): in offset_to_id()
135 case REG(DC_GPIO_GENLK_A): in offset_to_id()
159 case REG(DC_GPIO_DDC1_A): in offset_to_id()
162 case REG(DC_GPIO_DDC2_A): in offset_to_id()
165 case REG(DC_GPIO_DDC3_A): in offset_to_id()
168 case REG(DC_GPIO_DDC4_A): in offset_to_id()
171 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/
H A Damdgpu_hw_translate_dcn21.c59 #undef REG
60 #define REG(reg_name)\ macro
77 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
111 case REG(DC_GPIO_HPD_A): in offset_to_id()
138 case REG(DC_GPIO_GENLK_A): in offset_to_id()
162 case REG(DC_GPIO_DDC1_A): in offset_to_id()
165 case REG(DC_GPIO_DDC2_A): in offset_to_id()
168 case REG(DC_GPIO_DDC3_A): in offset_to_id()
171 case REG(DC_GPIO_DDC4_A): in offset_to_id()
174 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/netbsd-src/sys/arch/luna68k/stand/boot/
H A Dsio.c107 int rr0 = sioreg(REG(unit, RR0), 0); in siointr()
108 int rr1 = sioreg(REG(unit, RR1), 0); in siointr()
116 sioreg(REG(unit, WR0), WR0_ERRRST); in siointr()
191 while ((sioreg(REG(unit, RR0), 0) & RR0_TXEMPTY) == 0) in siocnputc()
197 while ((sioreg(REG(unit, RR0), 0) & RR0_TXEMPTY) == 0) in siocnputc()
216 sioreg(REG(0, WR0), WR0_CHANRST); in sioinit()
224 sioreg(REG(0, WR0), WR0_RSTINT); in sioinit()
226 sioreg(REG(0, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY); in sioinit()
228 sioreg(REG(0, WR3), WR3_RX8BIT | WR3_RXENBL); in sioinit()
230 sioreg(REG(0, WR5), WR5_TX8BIT | WR5_TXENBL | WR5_DTR | WR5_RTS); in sioinit()
[all …]
/netbsd-src/sys/dev/tc/
H A Dsfbplus.c73 #define REG(base, index) *((uint32_t *)(base) + (index)) macro
75 REG(vdac, bt_lo) = ((regno) & 0x00ff); \
76 REG(vdac, bt_hi) = ((regno) & 0x0f00) >> 8; \
611 REG(vdac, bt_reg) = 0x40; /* CMD0 */ tc_wmb(); in bt459init()
612 REG(vdac, bt_reg) = 0x0; /* CMD1 */ tc_wmb(); in bt459init()
613 REG(vdac, bt_reg) = 0xc0; /* CMD2 */ tc_wmb(); in bt459init()
614 REG(vdac, bt_reg) = 0xff; /* PRM */ tc_wmb(); in bt459init()
615 REG(vdac, bt_reg) = 0; /* 205 */ tc_wmb(); in bt459init()
616 REG(vdac, bt_reg) = 0x0; /* PBM */ tc_wmb(); in bt459init()
617 REG(vdac, bt_reg) = 0; /* 207 */ tc_wmb(); in bt459init()
[all …]
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Dcr16-opc.c466 #define REG(NAME, N, TYPE) {STRINGX(NAME), {(reg) NAME}, N, TYPE} macro
472 #define REG_R(N) REG(CONCAT2(r,N), N, CR16_R_REGTYPE)
478 REG(r12_L, 12, CR16_R_REGTYPE),
479 REG(r13_L, 13, CR16_R_REGTYPE),
480 REG(ra, 0xe, CR16_R_REGTYPE),
481 REG(sp, 0xf, CR16_R_REGTYPE),
482 REG(sp_L, 0xf, CR16_R_REGTYPE),
483 REG(RA, 0xe, CR16_R_REGTYPE),
494 REG((r12), 0xc, CR16_RP_REGTYPE),
495 REG((r13), 0xd, CR16_RP_REGTYPE),
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Dcr16-opc.c466 #define REG(NAME, N, TYPE) {STRINGX(NAME), {(reg) NAME}, N, TYPE} macro
472 #define REG_R(N) REG(CONCAT2(r,N), N, CR16_R_REGTYPE)
478 REG(r12_L, 12, CR16_R_REGTYPE),
479 REG(r13_L, 13, CR16_R_REGTYPE),
480 REG(ra, 0xe, CR16_R_REGTYPE),
481 REG(sp, 0xf, CR16_R_REGTYPE),
482 REG(sp_L, 0xf, CR16_R_REGTYPE),
483 REG(RA, 0xe, CR16_R_REGTYPE),
494 REG((r12), 0xc, CR16_RP_REGTYPE),
495 REG((r13), 0xd, CR16_RP_REGTYPE),
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_mpc.c38 #define REG(reg)\ macro
176 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); in mpc2_set_output_csc()
177 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); in mpc2_set_output_csc()
179 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); in mpc2_set_output_csc()
180 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); in mpc2_set_output_csc()
235 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); in mpc2_set_ocsc_default()
236 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); in mpc2_set_ocsc_default()
238 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); in mpc2_set_ocsc_default()
239 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); in mpc2_set_ocsc_default()
336 gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]); in mpc2_program_lutb()
[all …]
H A Damdgpu_dcn20_dpp_cm.c41 #define REG(reg)\ macro
200 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); in program_gamut_remap()
201 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); in program_gamut_remap()
203 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12); in program_gamut_remap()
204 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34); in program_gamut_remap()
296 icsc_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12); in dpp2_program_input_csc()
297 icsc_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34); in dpp2_program_input_csc()
301 icsc_regs.csc_c11_c12 = REG(CM_ICSC_B_C11_C12); in dpp2_program_input_csc()
302 icsc_regs.csc_c33_c34 = REG(CM_ICSC_B_C33_C34); in dpp2_program_input_csc()
400 gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B); in dpp20_program_blnd_luta_settings()
[all …]
/netbsd-src/sys/arch/arm/amlogic/
H A Dmeson8b_pinctrl.c50 #define REG 0x00 macro
491 { "uart_tx_ao_a", REG, 12, { GPIOAO_0 }, 1 },
492 { "uart_rx_ao_a", REG, 11, { GPIOAO_1 }, 1 },
493 { "uart_cts_ao_a", REG, 10, { GPIOAO_2 }, 1 },
494 { "uart_rts_ao_a", REG, 9, { GPIOAO_3 }, 1 },
495 { "i2c_mst_sck_ao", REG, 6, { GPIOAO_4 }, 1 },
496 { "i2c_mst_sda_ao", REG, 5, { GPIOAO_5 }, 1 },
497 { "clk_32k_in_out", REG, 18, { GPIOAO_6 }, 1 },
498 { "remote_input", REG, 0, { GPIOAO_7 }, 1 },
499 { "hdmi_cec_1", REG, 17, { GPIOAO_12 }, 1 },
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kInstrData.td41 /// 0 0 | SIZE | REG | MODE | MODE | REG
68 class MxMove_MR<MxOperand MEMOpd, ComplexPattern MEMPat, MxType REG,
70 : MxMove<REG.Prefix, (outs), (ins MEMOpd:$dst, REG.ROp:$src),
71 [(store REG.VT:$src, MEMPat:$dst)], ENC>;
85 class MxMove_RM<MxType REG, MxOperand MEMOpd, ComplexPattern MEMPat,
89 : MxMove<REG.Prefix, (outs REG.ROp:$dst), (ins MEMOpd:$src),
90 [(set REG.VT:$dst, (REG.Load MEMPat:$src))],
93 multiclass MMxMove_RM<MxType REG, MxMoveSize SIZE, MxEncEA EA_0> {
95 // REG <- (An)+
96 def NAME#REG.OOp.Letter#REG.Postfix : MxMove_RM<REG, REG.OOp, REG.OPat,
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gt/
H A Dintel_lrc.c552 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets() macro
618 REG(0x034),
619 REG(0x030),
620 REG(0x038),
621 REG(0x03c),
622 REG(0x168),
623 REG(0x140),
624 REG(0x110),
625 REG(0x11c),
626 REG(0x114),
[all …]
/netbsd-src/external/gpl3/gcc/dist/libgcc/config/alpha/
H A Dvms-gcc_shell_handler.c37 typedef unsigned long long REG; typedef
39 #define REG_AT(addr) (*(REG *)(addr))
56 get_dyn_handler_pointer (REG fp) in get_dyn_handler_pointer()
68 REG handler_slot_offset; in get_dyn_handler_pointer()
73 REG handler_data_offset; in get_dyn_handler_pointer()
99 handler_slot_offset = REG_AT ((REG)pd + handler_data_offset); in get_dyn_handler_pointer()
/netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/alpha/
H A Dvms-gcc_shell_handler.c37 typedef unsigned long long REG; typedef
39 #define REG_AT(addr) (*(REG *)(addr))
56 get_dyn_handler_pointer (REG fp) in get_dyn_handler_pointer()
68 REG handler_slot_offset; in get_dyn_handler_pointer()
73 REG handler_data_offset; in get_dyn_handler_pointer()
99 handler_slot_offset = REG_AT ((REG)pd + handler_data_offset); in get_dyn_handler_pointer()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
H A Dddc_regs.h37 .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\
51 .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)
55 .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\
56 .phy_aux_cntl = REG(PHY_AUX_CNTL), \
57 .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
60 .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\
77 .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\
96 .phy_aux_cntl = REG(PHY_AUX_CNTL), \
97 .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)

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