| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 156 MVT PartVT, EVT ValueVT, const Value *V,
166 MVT PartVT, EVT ValueVT, const Value *V, in getCopyFromParts() argument
172 PartVT, ValueVT, CC)) in getCopyFromParts()
176 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, in getCopyFromParts()
185 unsigned PartBits = PartVT.getSizeInBits(); in getCopyFromParts()
200 PartVT, HalfVT, V); in getCopyFromParts()
202 RoundParts / 2, PartVT, HalfVT, V); in getCopyFromParts()
217 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts, OddParts, PartVT, in getCopyFromParts()
233 } else if (PartVT.isFloatingPoint()) { in getCopyFromParts()
235 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && in getCopyFromParts()
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1535 EVT PartVT = VT; in getVectorTypeBreakdown() local
1538 LK = getTypeConversion(Context, PartVT); in getVectorTypeBreakdown()
1539 PartVT = LK.second; in getVectorTypeBreakdown()
1543 PartVT.getVectorElementCount().getKnownMinValue(); in getVectorTypeBreakdown()
1549 assert((PartVT.getVectorElementCount() * NumIntermediates) == in getVectorTypeBreakdown()
1552 IntermediateVT = PartVT; in getVectorTypeBreakdown()
1651 MVT PartVT = in GetReturnInfo() local
1666 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); in GetReturnInfo()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 462 unsigned NumParts, MVT PartVT,
468 MVT PartVT, EVT ValueVT,
|
| H A D | RISCVISelLowering.cpp | 7571 EVT PartVT = PartValue.getValueType(); in LowerCall() local
7572 StoredSize += PartVT.getStoreSize(); in LowerCall()
7573 StackAlign = std::max(StackAlign, getPrefTypeAlign(PartVT, DAG)); in LowerCall()
8526 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
8529 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
8541 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in splitValueIntoRegisterParts()
8544 EVT PartEltVT = PartVT.getVectorElementType(); in splitValueIntoRegisterParts()
8546 unsigned PartVTBitSize = PartVT.getSizeInBits().getKnownMinSize(); in splitValueIntoRegisterParts()
8557 Val = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), in splitValueIntoRegisterParts()
8568 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 866 SDValue *Parts, unsigned NumParts, MVT PartVT,
872 MVT PartVT, EVT ValueVT,
|
| H A D | ARMISelLowering.cpp | 4214 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
4218 PartVT == MVT::f32) { in splitValueIntoRegisterParts()
4220 unsigned PartBits = PartVT.getSizeInBits(); in splitValueIntoRegisterParts()
4223 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in splitValueIntoRegisterParts()
4232 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4235 PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
4237 unsigned PartBits = PartVT.getSizeInBits(); in joinRegisterPartsIntoValue()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3672 unsigned NumParts, MVT PartVT, in splitValueIntoRegisterParts() argument
3681 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 502 MVT PartVT = MVT::getVectorVT(VecTy.getVectorElementType(), OpsPerWord); in buildHvxVectorReg() local
504 SDValue W = buildVector32(Values.slice(i, OpsPerWord), dl, PartVT, DAG); in buildHvxVectorReg()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1594 MVT PartVT = getRegisterTypeForCallingConv(Ctx, CLI.CallConv, OrigArgVT); in LowerCall() local
1596 SlotVT = EVT::getIntegerVT(Ctx, PartVT.getSizeInBits() * N); in LowerCall()
|