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Searched refs:OtherVT (Results 1 – 25 of 43) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td154 def brtarget : Operand<OtherVT>;
268 def COND_OEQ : PatFrags<(ops), [(OtherVT SETOEQ), (OtherVT SETEQ)]>;
269 def COND_ONE : PatFrags<(ops), [(OtherVT SETONE), (OtherVT SETNE)]>;
270 def COND_OGT : PatFrags<(ops), [(OtherVT SETOGT), (OtherVT SETGT)]>;
271 def COND_OGE : PatFrags<(ops), [(OtherVT SETOGE), (OtherVT SETGE)]>;
272 def COND_OLT : PatFrags<(ops), [(OtherVT SETOLT), (OtherVT SETLT)]>;
273 def COND_OLE : PatFrags<(ops), [(OtherVT SETOLE), (OtherVT SETLE)]>;
274 def COND_O : PatFrags<(ops), [(OtherVT SETO)]>;
275 def COND_UO : PatFrags<(ops), [(OtherVT SETUO)]>;
281 def COND_UEQ : PatFrag<(ops), (OtherVT SETUEQ)>;
[all …]
H A DAMDGPUInstrInfo.td49 [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
53 [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
57 [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]
196 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
343 SDTCisVT<0, OtherVT>
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kInstrInfo.td80 /* Dest */ SDTCisVT<0, OtherVT>,
307 def MxAS8 : MxMemOp<(ops OtherVT), MxSize8, "B", "printAS8Mem", MxAddr>;
308 def MxAS16 : MxMemOp<(ops OtherVT), MxSize16, "B", "printAS16Mem", MxAddr>;
309 def MxAS32 : MxMemOp<(ops OtherVT), MxSize32, "B", "printAS32Mem", MxAddr>;
317 def MxAL8 : MxMemOp<(ops OtherVT), MxSize8, "b", "printAL8Mem", MxAddr>;
318 def MxAL16 : MxMemOp<(ops OtherVT), MxSize16, "b", "printAL16Mem", MxAddr>;
319 def MxAL32 : MxMemOp<(ops OtherVT), MxSize32, "b", "printAL32Mem", MxAddr>;
377 // Branch targets have OtherVT type and print as pc-relative values.
378 def MxBrTarget8 : Operand<OtherVT>;
379 def MxBrTarget16 : Operand<OtherVT>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZOperands.td542 def brtarget16 : PCRelOperand<OtherVT, PCRel16> {
546 def brtarget32 : PCRelOperand<OtherVT, PCRel32> {
552 def brtarget12bpp : PCRelOperand<OtherVT, PCRel12> {
556 def brtarget16bpp : PCRelOperand<OtherVT, PCRel16> {
560 def brtarget24bpp : PCRelOperand<OtherVT, PCRel24> {
568 def brtarget16tls : PCRelTLSOperand<OtherVT, PCRelTLS16> {
573 def brtarget32tls : PCRelTLSOperand<OtherVT, PCRelTLS32> {
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonDepOperands.td32 def b13_2Imm : Operand<OtherVT> { let ParserMatchClass = b13_2ImmOperand; let DecoderMethod = "brta…
35 def b15_2Imm : Operand<OtherVT> { let ParserMatchClass = b15_2ImmOperand; let DecoderMethod = "brta…
41 def b30_2Imm : Operand<OtherVT> { let ParserMatchClass = b30_2ImmOperand; let DecoderMethod = "brta…
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td108 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
168 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, OtherVT>
171 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
180 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
193 SDTCisVT<5, OtherVT>
197 SDTCisVT<0, OtherVT>
201 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
205 SDTCisInt<0>, SDTCisVT<1, OtherVT>
213 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>
301 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp455 for (MVT OtherVT : MVT::integer_scalable_vector_valuetypes()) { in RISCVTargetLowering() local
456 setTruncStoreAction(OtherVT, VT, Expand); in RISCVTargetLowering()
457 setLoadExtAction(ISD::EXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
458 setLoadExtAction(ISD::SEXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
459 setLoadExtAction(ISD::ZEXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
530 for (MVT OtherVT : MVT::integer_scalable_vector_valuetypes()) { in RISCVTargetLowering() local
531 setTruncStoreAction(VT, OtherVT, Expand); in RISCVTargetLowering()
532 setLoadExtAction(ISD::EXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
533 setLoadExtAction(ISD::SEXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
534 setLoadExtAction(ISD::ZEXTLOAD, OtherVT, VT, Expand); in RISCVTargetLowering()
[all …]
H A DRISCVInstrInfo.td29 SDTCisVT<2, OtherVT>,
30 SDTCisVT<3, OtherVT>]>;
177 def simm13_lsb0 : Operand<OtherVT> {
216 def simm21_lsb0_jal : Operand<OtherVT> {
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMicroMipsInstrInfo.td164 def jmptarget_mm : Operand<OtherVT> {
172 def brtarget7_mm : Operand<OtherVT> {
179 def brtarget10_mm : Operand<OtherVT> {
186 def brtarget_mm : Operand<OtherVT> {
H A DMips32r6InstrInfo.td37 def brtarget21 : Operand<OtherVT> {
44 def brtarget26 : Operand<OtherVT> {
51 def jmpoffset16 : Operand<OtherVT> {
H A DMicroMips32r6InstrInfo.td13 def brtarget21_mm : Operand<OtherVT> {
20 def brtarget26_mm : Operand<OtherVT> {
27 def brtargetr6 : Operand<OtherVT> {
34 def brtarget_lsl2_mm : Operand<OtherVT> {
H A DMipsInstrInfo.td833 def jmptarget : Operand<OtherVT> {
837 def brtarget : Operand<OtherVT> {
843 def brtarget1SImm16 : Operand<OtherVT> {
935 def uimm5_lsl2 : Operand<OtherVT> {
946 def uimm6_lsl2 : Operand<OtherVT> {
1045 def simm7_lsl2 : Operand<OtherVT> {
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td162 // Branch targets have OtherVT type.
163 def brtarget : Operand<OtherVT> {
167 def bprtarget : Operand<OtherVT> {
171 def bprtarget16 : Operand<OtherVT> {
200 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCInstrFormats.td896 def btarget : BCTarget<OtherVT>;
902 class BranchTargetS<int BSz> : BCTargetSigned<OtherVT, BSz>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp275 EVT OtherVT = N->getValueType(OtherNo); in ScalarizeVecRes_OverflowOp() local
276 if (getTypeAction(OtherVT) == TargetLowering::TypeScalarizeVector) { in ScalarizeVecRes_OverflowOp()
280 ISD::SCALAR_TO_VECTOR, DL, OtherVT, SDValue(ScalarNode, OtherNo)); in ScalarizeVecRes_OverflowOp()
1552 EVT OtherVT = N->getValueType(OtherNo); in SplitVecRes_OverflowOp() local
1553 if (getTypeAction(OtherVT) == TargetLowering::TypeSplitVector) { in SplitVecRes_OverflowOp()
1558 ISD::CONCAT_VECTORS, dl, OtherVT, in SplitVecRes_OverflowOp()
3506 EVT OtherVT = N->getValueType(OtherNo); in WidenVecRes_OverflowOp() local
3507 if (getTypeAction(OtherVT) == TargetLowering::TypeWidenVector) { in WidenVecRes_OverflowOp()
3512 ISD::EXTRACT_SUBVECTOR, DL, OtherVT, SDValue(WideNode, OtherNo), Zero); in WidenVecRes_OverflowOp()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td31 def SDT_MSP430BrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>,
118 // Short jump targets have OtherVT type and are printed as pcrel imm values.
119 def jmptarget : Operand<OtherVT> {
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.td136 def bb_op : Operand<OtherVT>;
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DValueTypes.td21 def OtherVT : ValueType<0, 1>; // "Other" value
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrThumb.td128 def t_brtarget : Operand<OtherVT> {
141 def thumb_br_target : Operand<OtherVT> {
160 def thumb_bcc_target : Operand<OtherVT> {
166 def thumb_cb_target : Operand<OtherVT> {
H A DARMInstrFormats.td157 def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
176 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
184 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
251 class vpred_ops<dag extra_op, dag extra_mi> : OperandWithDefaultOps<OtherVT,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td34 def SDT_LanaiBrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>,
89 def BrTarget : Operand<OtherVT> {
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td27 SDTCisVT<3, OtherVT>]>;
57 def brtarget : Operand<OtherVT> {
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td24 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
193 def relbrtarget_7 : Operand<OtherVT>
199 def brtarget_13 : Operand<OtherVT>
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DIntrinsics.td194 : LLVMType<OtherVT>{
254 def llvm_empty_ty : LLVMType<OtherVT>; // { }

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