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Searched refs:NewMask (Results 1 – 25 of 30) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DRegisterPressure.cpp52 LaneBitmask PrevMask, LaneBitmask NewMask) { in increaseSetPressure() argument
53 assert((PrevMask & ~NewMask).none() && "Must not remove bits"); in increaseSetPressure()
54 if (PrevMask.any() || NewMask.none()) in increaseSetPressure()
66 LaneBitmask PrevMask, LaneBitmask NewMask) { in decreaseSetPressure() argument
68 if (NewMask.any() || PrevMask.none()) in decreaseSetPressure()
157 LaneBitmask NewMask) { in increaseRegPressure() argument
158 if (PreviousMask.any() || NewMask.none()) in increaseRegPressure()
172 LaneBitmask NewMask) { in decreaseRegPressure() argument
173 decreaseSetPressure(CurrSetPressure, *MRI, RegUnit, PreviousMask, NewMask); in decreaseRegPressure()
710 LaneBitmask NewMask = PrevMask | P.LaneMask; in addLiveRegs() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.cpp86 LaneBitmask NewMask, in inc() argument
88 if (SIRegisterInfo::getNumCoveredRegs(NewMask) == in inc()
93 if (NewMask < PrevMask) { in inc()
94 std::swap(NewMask, PrevMask); in inc()
108 assert(PrevMask < NewMask); in inc()
111 Sign * SIRegisterInfo::getNumCoveredRegs(~PrevMask & NewMask); in inc()
114 assert(NewMask.any()); in inc()
H A DSIModeRegister.cpp36 Status(unsigned NewMask, unsigned NewMode) : Mask(NewMask), Mode(NewMode) { in Status()
55 unsigned NewMask = (Mask & S.Mask) & (Mode ^ ~S.Mode); in intersect() local
56 unsigned NewMode = (Mode & NewMask); in intersect()
57 return Status(NewMask, NewMode); in intersect()
H A DAMDGPUInstructionSelector.cpp2775 static Register normalizeVOP3PMask(int NewMask[2], Register Src0, Register Src1, in normalizeVOP3PMask()
2777 NewMask[0] = Mask[0]; in normalizeVOP3PMask()
2778 NewMask[1] = Mask[1]; in normalizeVOP3PMask()
2782 assert(NewMask[0] == 2 || NewMask[0] == 3 || NewMask[0] == -1); in normalizeVOP3PMask()
2783 assert(NewMask[1] == 2 || NewMask[1] == 3 || NewMask[1] == -1); in normalizeVOP3PMask()
2786 NewMask[0] = NewMask[0] == -1 ? -1 : NewMask[0] - 2; in normalizeVOP3PMask()
2787 NewMask[1] = NewMask[1] == -1 ? -1 : NewMask[1] - 2; in normalizeVOP3PMask()
H A DGCNRegPressure.h70 LaneBitmask NewMask,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kCollapseMOVEMPass.cpp93 UpdateType classifyUpdateByMask(unsigned NewMask) const { in classifyUpdateByMask()
94 assert(NewMask && "Mask needs to select at least one register"); in classifyUpdateByMask()
96 if (NewMask > Mask) { in classifyUpdateByMask()
98 } else if (NewMask < Mask) { in classifyUpdateByMask()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp1155 SmallVector<int, 16> NewMask(NumMaskElts); in foldInsEltIntoSplat() local
1157 NewMask[i] = i == IdxC ? 0 : Shuf->getMaskValue(i); in foldInsEltIntoSplat()
1159 return new ShuffleVectorInst(Op0, UndefValue::get(Op0->getType()), NewMask); in foldInsEltIntoSplat()
1194 SmallVector<int, 16> NewMask(NumMaskElts); in foldInsEltIntoIdentityShuffle() local
1199 NewMask[i] = OldMask[i]; in foldInsEltIntoIdentityShuffle()
1207 NewMask[i] = IdxC; in foldInsEltIntoIdentityShuffle()
1211 return new ShuffleVectorInst(X, Shuf->getOperand(1), NewMask); in foldInsEltIntoIdentityShuffle()
1871 SmallVector<int, 16> NewMask(NumMaskElts, 0); in canonicalizeInsertSplat() local
1874 NewMask[i] = Mask[i]; in canonicalizeInsertSplat()
1876 return new ShuffleVectorInst(NewIns, UndefVec, NewMask); in canonicalizeInsertSplat()
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H A DInstCombineShifts.cpp223 Constant *NewMask; in dropRedundantMaskingOfLeftShiftInput() local
254 NewMask = ConstantExpr::getNot(ExtendedInvertedMask); in dropRedundantMaskingOfLeftShiftInput()
290 NewMask = in dropRedundantMaskingOfLeftShiftInput()
295 NewMask = ConstantExpr::getTrunc(NewMask, NarrowestTy); in dropRedundantMaskingOfLeftShiftInput()
298 bool NeedMask = !match(NewMask, m_AllOnes()); in dropRedundantMaskingOfLeftShiftInput()
323 return BinaryOperator::Create(Instruction::And, NewShift, NewMask); in dropRedundantMaskingOfLeftShiftInput()
H A DInstCombineAndOrXor.cpp236 unsigned NewMask; in conjugateICmpMask() local
237 NewMask = (Mask & (AMask_AllOnes | BMask_AllOnes | Mask_AllZeros | in conjugateICmpMask()
241 NewMask |= (Mask & (AMask_NotAllOnes | BMask_NotAllOnes | Mask_NotAllZeros | in conjugateICmpMask()
245 return NewMask; in conjugateICmpMask()
458 Value *NewMask = ConstantInt::get(BCst->getType(), BorD); in foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed() local
460 Value *NewAnd = Builder.CreateAnd(A, NewMask); in foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed()
632 APInt NewMask = BCst->getValue() & DCst->getValue(); in foldLogOpOfMaskedICmps() local
634 if (NewMask == BCst->getValue()) in foldLogOpOfMaskedICmps()
636 else if (NewMask == DCst->getValue()) in foldLogOpOfMaskedICmps()
645 APInt NewMask = BCst->getValue() | DCst->getValue(); in foldLogOpOfMaskedICmps() local
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H A DInstCombineSimplifyDemanded.cpp298 APInt NewMask = ~(LHSKnown.One & RHSKnown.One & DemandedMask); in SimplifyDemandedUseBits() local
301 ConstantInt::get(I->getType(), NewMask & AndRHS->getValue()); in SimplifyDemandedUseBits()
306 ConstantInt::get(I->getType(), NewMask & XorRHS->getValue()); in SimplifyDemandedUseBits()
H A DInstructionCombining.cpp1742 SmallVector<int, 8> NewMask(MaskC.size(), SplatIndex); in foldVectorBinop() local
1743 Value *NewSplat = Builder.CreateShuffleVector(NewBO, NewMask); in foldVectorBinop()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp848 MutableArrayRef<int> NewMask, unsigned Options = None);
850 MutableArrayRef<int> NewMask);
1033 ResultStack &Results, MutableArrayRef<int> NewMask, in packs() argument
1059 memcpy(NewMask.data(), SM.Mask.data(), sizeof(int)*VecLen); in packs()
1067 NewMask[I] = M; in packs()
1097 NewMask[I] = M; in packs()
1120 NewMask[I] = M; in packs()
1130 ResultStack &Results, MutableArrayRef<int> NewMask) { in packp() argument
1172 NewMask[I] = M; in packp()
1229 SmallVector<int,128> NewMask(VecLen); in shuffs2() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
H A DVectorCombine.cpp526 SmallVector<int, 16> NewMask; in foldBitcastShuf() local
532 narrowShuffleMaskElts(ScaleFactor, Mask, NewMask); in foldBitcastShuf()
538 if (!widenShuffleMaskElts(ScaleFactor, Mask, NewMask)) in foldBitcastShuf()
545 TargetTransformInfo::SK_PermuteSingleSrc, DestTy, NewMask); in foldBitcastShuf()
554 Value *Shuf = Builder.CreateShuffleVector(CastV, NewMask); in foldBitcastShuf()
H A DSLPVectorizer.cpp3776 SmallVector<int> NewMask; in getEntryCost() local
3777 inversePermutation(E->ReorderIndices, NewMask); in getEntryCost()
3779 TargetTransformInfo::SK_PermuteSingleSrc, VecTy, NewMask); in getEntryCost()
4045 SmallVector<int> NewMask; in getEntryCost() local
4046 inversePermutation(E->ReorderIndices, NewMask); in getEntryCost()
4048 TargetTransformInfo::SK_PermuteSingleSrc, VecTy, NewMask); in getEntryCost()
4065 SmallVector<int> NewMask; in getEntryCost() local
4066 inversePermutation(E->ReorderIndices, NewMask); in getEntryCost()
4068 TargetTransformInfo::SK_PermuteSingleSrc, VecTy, NewMask); in getEntryCost()
4809 SmallVector<int, 4> NewMask; in addInversedMask() local
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DRegisterPressure.h552 LaneBitmask NewMask);
554 LaneBitmask NewMask);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/
H A DIntrinsicInst.cpp302 void VPIntrinsic::setMaskParam(Value *NewMask) { in setMaskParam() argument
304 setArgOperand(*MaskPos, NewMask); in setMaskParam()
H A DInstructions.cpp1971 SmallVector<int, 16> NewMask(NumMaskElts); in commute() local
1975 NewMask[i] = UndefMaskElem; in commute()
1980 NewMask[i] = MaskElt; in commute()
1982 setShuffleMask(NewMask); in commute()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1853 SDValue NewMask = DAG.getConstant(0xff, DL, VT); in foldMaskAndShiftToExtract() local
1855 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask); in foldMaskAndShiftToExtract()
1866 insertDAGNode(DAG, N, NewMask); in foldMaskAndShiftToExtract()
1925 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT); in foldMaskedShiftToScaledMask() local
1926 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask); in foldMaskedShiftToScaledMask()
1934 insertDAGNode(DAG, N, NewMask); in foldMaskedShiftToScaledMask()
2091 SDValue NewMask = DAG.getConstant(Mask >> AMShiftAmt, DL, VT); in foldMaskedShiftToBEXTR() local
2092 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, NewSRL, NewMask); in foldMaskedShiftToBEXTR()
2103 insertDAGNode(DAG, N, NewMask); in foldMaskedShiftToBEXTR()
4300 SDValue NewMask = CurDAG->getConstant(NegMaskVal, SDLoc(And), VT); in shrinkAndImmediate() local
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H A DX86ISelLowering.cpp13601 SmallVector<int, 4> NewMask(Mask.begin(), Mask.end()); in lowerShuffleOfExtractsAsVperm() local
13605 ShuffleVectorSDNode::commuteMask(NewMask); in lowerShuffleOfExtractsAsVperm()
13613 (isSingleSHUFPSMask(NewMask) || is128BitUnpackShuffleMask(NewMask))) in lowerShuffleOfExtractsAsVperm()
13617 NewMask.append(NumElts, -1); in lowerShuffleOfExtractsAsVperm()
13621 NewMask); in lowerShuffleOfExtractsAsVperm()
14240 SmallVector<int, 4> NewMask(Mask.begin(), Mask.end()); in lowerShuffleWithSHUFPS() local
14256 NewMask[V2Index] -= 4; in lowerShuffleWithSHUFPS()
14273 NewMask[V1Index] = 2; // We put the V1 element in V2[2]. in lowerShuffleWithSHUFPS()
14274 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0]. in lowerShuffleWithSHUFPS()
14280 NewMask[2] -= 4; in lowerShuffleWithSHUFPS()
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H A DX86InstrInfo.cpp7377 unsigned NewMask = 0; in AdjustBlendMask() local
7385 NewMask |= (1u << i); in AdjustBlendMask()
7394 NewMask |= (SubMask << (i * Scale)); in AdjustBlendMask()
7400 *pNewMask = NewMask; in AdjustBlendMask()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp268 SmallVector<int, 8> NewMask; in ShuffleWithNarrowerEltType() local
273 NewMask.push_back(-1); in ShuffleWithNarrowerEltType()
275 NewMask.push_back(Idx * NumEltsGrowth + j); in ShuffleWithNarrowerEltType()
278 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); in ShuffleWithNarrowerEltType()
279 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); in ShuffleWithNarrowerEltType()
280 return DAG.getVectorShuffle(NVT, dl, N1, N2, NewMask); in ShuffleWithNarrowerEltType()
2999 SmallVector<int, 32> NewMask; in ExpandNode() local
3037 NewMask.push_back(Mask[i]); in ExpandNode()
3041 NewMask.push_back(Mask[i]*factor+fi); in ExpandNode()
3044 Mask = NewMask; in ExpandNode()
H A DDAGCombiner.cpp5178 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT); in visitANDLike() local
5181 SDValue And = DAG.getNode(ISD::AND, SL, HalfVT, Shift, NewMask); in visitANDLike()
12664 SmallVector<int, 8> NewMask; in visitBITCAST() local
12667 NewMask.push_back(M < 0 ? -1 : M * MaskScale + i); in visitBITCAST()
12670 TLI.buildLegalVectorShuffle(VT, SDLoc(N), SV0, SV1, NewMask, DAG); in visitBITCAST()
18212 SmallVector<int, 16> NewMask(Mask.begin(), Mask.end()); in combineInsertEltToShuffle() local
18215 NewMask[InsIndex] = ElementOffset + ExtrIndex->getZExtValue(); in combineInsertEltToShuffle()
18216 assert(NewMask[InsIndex] < in combineInsertEltToShuffle()
18218 NewMask[InsIndex] >= 0 && "NewMask[InsIndex] is out of bound"); in combineInsertEltToShuffle()
18222 Y, NewMask, DAG); in combineInsertEltToShuffle()
[all …]
H A DLegalizeVectorTypes.cpp4409 SmallVector<int, 16> NewMask; in WidenVecRes_VECTOR_SHUFFLE() local
4413 NewMask.push_back(Idx); in WidenVecRes_VECTOR_SHUFFLE()
4415 NewMask.push_back(Idx - NumElts + WidenNumElts); in WidenVecRes_VECTOR_SHUFFLE()
4418 NewMask.push_back(-1); in WidenVecRes_VECTOR_SHUFFLE()
4419 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, NewMask); in WidenVecRes_VECTOR_SHUFFLE()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp6004 auto UseMask = [Mask, Op, VT, &TLO](const APInt &NewMask) -> bool { in targetShrinkDemandedConstant() argument
6005 if (NewMask == Mask) in targetShrinkDemandedConstant()
6008 SDValue NewC = TLO.DAG.getConstant(NewMask, DL, VT); in targetShrinkDemandedConstant()
6020 APInt NewMask = APInt(Mask.getBitWidth(), 0xffff); in targetShrinkDemandedConstant() local
6021 if (IsLegalMask(NewMask)) in targetShrinkDemandedConstant()
6022 return UseMask(NewMask); in targetShrinkDemandedConstant()
6027 APInt NewMask = APInt(64, 0xffffffff); in targetShrinkDemandedConstant() local
6028 if (IsLegalMask(NewMask)) in targetShrinkDemandedConstant()
6029 return UseMask(NewMask); in targetShrinkDemandedConstant()
6042 APInt NewMask = ShrunkMask; in targetShrinkDemandedConstant() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp344 unsigned NewMask = 0; in rewindImplicitITPosition() local
345 NewMask |= ITState.Mask & (0xC << TZ); in rewindImplicitITPosition()
346 NewMask |= 0x2 << TZ; in rewindImplicitITPosition()
347 ITState.Mask = NewMask; in rewindImplicitITPosition()
392 unsigned NewMask = 0; in extendImplicitITBlock() local
394 NewMask |= ITState.Mask & (0xE << TZ); in extendImplicitITBlock()
396 NewMask |= (Cond != ITState.Cond) << TZ; in extendImplicitITBlock()
398 NewMask |= 1 << (TZ - 1); in extendImplicitITBlock()
399 ITState.Mask = NewMask; in extendImplicitITBlock()

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