| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VVPInstrPatternsVec.td | 22 ValueType ScalarVT, ValueType DataVT, ValueType MaskVT,
28 DataVT:$vy, (MaskVT true_mask), i32:$avl),
31 def : Pat<(OpNode DataVT:$vx, DataVT:$vy, (MaskVT true_mask), i32:$avl),
38 DataVT:$vy, MaskVT:$mask, i32:$avl),
41 def : Pat<(OpNode DataVT:$vx, DataVT:$vy, MaskVT:$mask, i32:$avl),
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| H A D | VEISelLowering.cpp | 2698 MVT MaskVT = MVT::v256i1; // TODO: packed mode. in lowerToVVP() local
2716 Mask = DAG.getNode(VEISD::VEC_BROADCAST, DL, MaskVT, in lowerToVVP()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 8867 MVT MaskVT = BOperand.getSimpleValueType(); in lowerBuildVectorAsBroadcast() local
8869 if ((EltType == MVT::i64 && MaskVT == MVT::v8i1) || // for broadcastmb2q in lowerBuildVectorAsBroadcast()
8870 (EltType == MVT::i32 && MaskVT == MVT::v16i1)) { // for broadcastmw2d in lowerBuildVectorAsBroadcast()
11369 static SDValue getMaskNode(SDValue Mask, MVT MaskVT,
11914 MVT MaskVT = VT; in lowerShuffleAsBitMask() local
11920 MaskVT = MVT::getVectorVT(EltVT, Mask.size()); in lowerShuffleAsBitMask()
11953 SDValue VMask = DAG.getBuildVector(MaskVT, DL, VMaskOps); in lowerShuffleAsBitMask()
15278 MVT MaskVT = VT.changeTypeToInteger(); in lowerShuffleWithPERMV() local
15293 MaskNode = getConstVector(AdjustedMask, MaskVT, DAG, DL, true); in lowerShuffleWithPERMV()
15296 MaskNode = getConstVector(Mask, MaskVT, DAG, DL, true); in lowerShuffleWithPERMV()
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| H A D | X86ISelDAGToDAG.cpp | 4458 MVT MaskVT = ResVT; in tryVPTESTM() local
4465 MaskVT = MVT::getVectorVT(MVT::i1, NumElts); in tryVPTESTM()
4475 unsigned RegClass = TLI->getRegClassFor(MaskVT)->getID(); in tryVPTESTM()
4478 dl, MaskVT, InMask, RC), 0); in tryVPTESTM()
4488 SDVTList VTs = CurDAG->getVTList(MaskVT, MVT::Other); in tryVPTESTM()
4506 CNode = CurDAG->getMachineNode(Opc, dl, MaskVT, InMask, Src0, Src1); in tryVPTESTM()
4508 CNode = CurDAG->getMachineNode(Opc, dl, MaskVT, Src0, Src1); in tryVPTESTM()
5722 MVT MaskVT = Mask.getSimpleValueType(); in Select() local
5727 if (!ValueVT.isVector() || !MaskVT.isVector()) in Select()
5737 bool AVX512Gather = MaskVT.getVectorElementType() == MVT::i1; in Select()
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| H A D | X86InstrSSE.td | 7798 ValueType MaskVT> {
7800 def: Pat<(masked_store (VT RC:$src), addr:$ptr, (MaskVT RC:$mask)),
7803 def: Pat<(VT (masked_load addr:$ptr, (MaskVT RC:$mask), undef)),
7805 def: Pat<(VT (masked_load addr:$ptr, (MaskVT RC:$mask),
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 4055 EVT MaskVT = Mask.getValueType(); in WidenVecRes_MLOAD() local
4062 MaskVT.getVectorElementType(), in WidenVecRes_MLOAD()
4080 EVT MaskVT = Mask.getValueType(); in WidenVecRes_MGATHER() local
4088 MaskVT.getVectorElementType(), in WidenVecRes_MGATHER()
4177 SDValue DAGTypeLegalizer::convertMask(SDValue InMask, EVT MaskVT, in convertMask() argument
4191 { MaskVT, MVT::Other }, Ops); in convertMask()
4195 Mask = DAG.getNode(InMask->getOpcode(), SDLoc(InMask), MaskVT, Ops); in convertMask()
4200 unsigned MaskScalarBits = MaskVT.getScalarSizeInBits(); in convertMask()
4204 MaskVT.getVectorNumElements()); in convertMask()
4208 MaskVT.getVectorNumElements()); in convertMask()
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| H A D | LegalizeTypes.h | 985 SDValue convertMask(SDValue InMask, EVT MaskVT, EVT ToMaskVT);
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| H A D | TargetLowering.cpp | 7743 EVT MaskVT = Mask.getValueType(); in IncrementMemoryAddress() local
7744 assert(DataVT.getVectorElementCount() == MaskVT.getVectorElementCount() && in IncrementMemoryAddress()
7751 EVT MaskIntVT = EVT::getIntegerVT(*DAG.getContext(), MaskVT.getSizeInBits()); in IncrementMemoryAddress()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1286 MVT MaskVT = MVT::getVectorVT(MVT::i1, ContainerVT.getVectorElementCount()); in getDefaultVLOps() local
1287 SDValue Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL); in getDefaultVLOps()
1834 MVT MaskVT = MVT::getVectorVT(MVT::i1, NumElts); in lowerVECTOR_SHUFFLE() local
1835 SDValue SelectMask = DAG.getBuildVector(MaskVT, DL, MaskVals); in lowerVECTOR_SHUFFLE()
3059 EVT MaskVT = Op.getValueType(); in lowerVectorMaskTrunc() local
3061 assert(MaskVT.isVector() && MaskVT.getVectorElementType() == MVT::i1 && in lowerVectorMaskTrunc()
3081 return DAG.getSetCC(DL, MaskVT, Trunc, SplatZero, ISD::SETNE); in lowerVectorMaskTrunc()
3092 return convertFromScalableVector(MaskVT, Trunc, DAG, Subtarget); in lowerVectorMaskTrunc()
3226 MVT MaskVT = MVT::getVectorVT(MVT::i1, ContainerVT.getVectorElementCount()); in lowerEXTRACT_VECTOR_ELT() local
3227 SDValue Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL); in lowerEXTRACT_VECTOR_ELT()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | BasicTTIImpl.h | 1249 auto *MaskVT = FixedVectorType::get(I8Type, NumElts);
1268 thisT()->getVectorInstrCost(Instruction::InsertElement, MaskVT, i);
1276 Cost += thisT()->getArithmeticInstrCost(BinaryOperator::And, MaskVT,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 17301 MVT MaskVT; in getPredicateForFixedLengthVector() local
17306 MaskVT = MVT::nxv16i1; in getPredicateForFixedLengthVector()
17310 MaskVT = MVT::nxv8i1; in getPredicateForFixedLengthVector()
17314 MaskVT = MVT::nxv4i1; in getPredicateForFixedLengthVector()
17318 MaskVT = MVT::nxv2i1; in getPredicateForFixedLengthVector()
17322 return DAG.getNode(AArch64ISD::PTRUE, DL, MaskVT, in getPredicateForFixedLengthVector()
17834 EVT MaskVT = Op.getOperand(0).getValueType(); in LowerFixedLengthVectorSelectToSVE() local
17835 EVT MaskContainerVT = getContainerForFixedLengthVector(DAG, MaskVT); in LowerFixedLengthVectorSelectToSVE()
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