| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTDC.cpp | 297 int Mask0, Mask1; in convertLogicOp() local
300 std::tie(Op1, Mask1, Worthy1) = ConvertedInsts[cast<Instruction>(I.getOperand(1))]; in convertLogicOp()
306 Mask = Mask0 & Mask1; in convertLogicOp()
309 Mask = Mask0 | Mask1; in convertLogicOp()
312 Mask = Mask0 ^ Mask1; in convertLogicOp()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| H A D | EarlyCSE.cpp | 861 auto IsSubmask = [](const Value *Mask0, const Value *Mask1) { in isNonTargetIntrinsicMatch() argument
863 if (Mask0 == Mask1) in isNonTargetIntrinsicMatch()
865 if (isa<UndefValue>(Mask0) || isa<UndefValue>(Mask1)) in isNonTargetIntrinsicMatch()
868 auto *Vec1 = dyn_cast<ConstantVector>(Mask1); in isNonTargetIntrinsicMatch()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMSystemRegister.td | 45 // Mask1 Mask2 Mask3 Enc12, Name
|
| H A D | ARMISelLowering.cpp | 5790 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32); in LowerFCOPYSIGN() local
5792 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); in LowerFCOPYSIGN()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 1590 uint64_t Mask1 = computeKnownBits(Mask, 0, II).One.getZExtValue(); in visitCallInst() local
1592 uint64_t C = Bytes1 & Mask1; in visitCallInst()
|
| H A D | InstCombineCompares.cpp | 3121 APInt Mask1 = IsTrailing ? APInt::getLowBitsSet(BitWidth, Num + 1) in foldICmpEqIntrinsicWithConstant() local
3127 Builder.CreateAnd(II->getArgOperand(0), Mask1), in foldICmpEqIntrinsicWithConstant()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6183 ConstantSDNode *Mask1 = isConstOrConstSplat(N1.getOperand(1)); in matchBSwapHWordOrAndAnd() local
6184 if (!Mask0 || !Mask1) in matchBSwapHWordOrAndAnd()
6187 Mask1->getAPIntValue() != 0x00ff00ff) in matchBSwapHWordOrAndAnd()
20372 SmallVector<int, 16> Mask1(HalfNumElts, -1); in foldShuffleOfConcatUndefs() local
20380 Mask1[i - HalfNumElts] = M; in foldShuffleOfConcatUndefs()
20388 !TLI.isShuffleMaskLegal(Mask1, HalfVT)) in foldShuffleOfConcatUndefs()
20396 SDValue Shuf1 = DAG.getVectorShuffle(HalfVT, DL, X, Y, Mask1); in foldShuffleOfConcatUndefs()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 5630 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); in lowerU64ToF32BitOps() local
5631 auto T = MIRBuilder.buildAnd(S64, U, Mask1); in lowerU64ToF32BitOps()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 7585 SmallVector<int, 64> Mask0, Mask1; in getFauxShuffleMask() local
7587 narrowShuffleMaskElts(MaskSize / SrcMask1.size(), SrcMask1, Mask1); in getFauxShuffleMask()
7593 if (Mask0[i] == SM_SentinelZero && Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
7595 else if (Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
43532 SmallVector<int> Mask0, Mask1, ScaledMask0, ScaledMask1; in combineHorizOpWithShuffle() local
43538 getTargetShuffleInputs(BC1, Ops1, Mask1, DAG) && !isAnyZero(Mask1) && in combineHorizOpWithShuffle()
43539 scaleShuffleElements(Mask1, 2, ScaledMask1) && in combineHorizOpWithShuffle()
43586 SmallVector<int> Mask0, Mask1; in combineHorizOpWithShuffle() local
43590 getTargetShuffleInputs(BC1, Ops1, Mask1, DAG) && !isAnyZero(Mask1) && in combineHorizOpWithShuffle()
43597 scaleShuffleElements(Mask1, 2, ScaledMask1)) { in combineHorizOpWithShuffle()
|