| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 114 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
169 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
217 setOperationAction(ISD::MLOAD, BoolW, Custom); in initializeHVXLowering()
1711 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE); in LowerHvxMaskedOp()
1713 if (Opc == ISD::MLOAD) { in LowerHvxMaskedOp()
1843 assert(MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE); in SplitHvxMemOp()
1850 if (MemOpc == ISD::MLOAD) { in SplitHvxMemOp()
2068 case ISD::MLOAD: in LowerHvxOperation()
2121 case ISD::MLOAD: in LowerHvxOperation()
2166 case ISD::MLOAD: in LowerHvxOperationWrapper()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGNodes.h | 1384 N->getOpcode() == ISD::MLOAD ||
2327 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2330 return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
2346 return N->getOpcode() == ISD::MLOAD ||
2359 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
2374 return N->getOpcode() == ISD::MLOAD;
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| H A D | ISDOpcodes.h | 1146 MLOAD, enumerator
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 387 case ISD::MLOAD: return "masked_load"; in getOperationName()
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| H A D | LegalizeVectorTypes.cpp | 938 case ISD::MLOAD: in SplitVectorResult()
3000 case ISD::MLOAD: in WidenVectorResult()
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| H A D | LegalizeIntegerTypes.cpp | 72 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N)); in PromoteIntegerResult()
1510 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N), in PromoteIntegerOperand()
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| H A D | SelectionDAG.cpp | 685 case ISD::MLOAD: { in AddNodeIDCustom()
7549 AddNodeIDNode(ID, ISD::MLOAD, VTs, Ops); in getMaskedLoad()
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| H A D | DAGCombiner.cpp | 1719 case ISD::MLOAD: return visitMLOAD(N); in visit()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 515 setOperationAction(ISD::MLOAD, VT, Custom); in RISCVTargetLowering()
576 setOperationAction(ISD::MLOAD, VT, Custom); in RISCVTargetLowering()
676 setOperationAction(ISD::MLOAD, VT, Custom); in RISCVTargetLowering()
755 setOperationAction(ISD::MLOAD, VT, Custom); in RISCVTargetLowering()
2333 case ISD::MLOAD: in LowerOperation()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1440 case ISD::MLOAD: in SelectT2AddrModeImm7Offset()
3795 case ISD::MLOAD: in Select()
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| H A D | ARMISelLowering.cpp | 274 setOperationAction(ISD::MLOAD, VT, Custom); in addMVEVectorTypes()
339 setOperationAction(ISD::MLOAD, VT, Custom); in addMVEVectorTypes()
9923 case ISD::MLOAD: in LowerOperation()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 650 def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1198 setOperationAction(ISD::MLOAD, VT, Custom); in AArch64TargetLowering()
1489 setOperationAction(ISD::MLOAD, VT, Custom); in addTypeForFixedLengthSVE()
4677 case ISD::MLOAD: in LowerOperation()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1402 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
1582 setOperationAction(ISD::MLOAD, VT, Custom); in X86TargetLowering()
1736 setOperationAction(ISD::MLOAD, VT, Legal); in X86TargetLowering()
1743 setOperationAction(ISD::MLOAD, VT, Legal); in X86TargetLowering()
1889 setOperationAction(ISD::MLOAD, VT, Subtarget.hasVLX() ? Legal : Custom); in X86TargetLowering()
2030 setTargetDAGCombine(ISD::MLOAD); in X86TargetLowering()
30389 case ISD::MLOAD: return LowerMLOAD(Op, Subtarget, DAG); in LowerOperation()
50829 case ISD::MLOAD: return combineMaskedLoad(N, DAG, DCI, Subtarget); in PerformDAGCombine()
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