| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 68 const DebugLoc &DL, unsigned Reg, unsigned Lane,
74 unsigned Lane, const TargetRegisterClass *TRC);
88 unsigned Lane, unsigned ToInsert);
418 unsigned Lane, bool QPR) { in createDupLane() argument
424 .addImm(Lane) in createDupLane()
433 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument
440 .addReg(DReg, 0, Lane); in createExtractSubreg()
478 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg() argument
486 .addImm(Lane); in createInsertSubreg()
543 unsigned Lane; in optimizeAllLanesPattern() local
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| /netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| H A D | armada-xp-db.dts | 192 /* Port 0, Lane 0 */
196 /* Port 0, Lane 1 */
200 /* Port 0, Lane 2 */
204 /* Port 0, Lane 3 */
208 /* Port 2, Lane 0 */
212 /* Port 3, Lane 0 */
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| H A D | armada-xp-axpwifiap.dts | 102 /* Port 0, Lane 0 */
108 /* Port 0, Lane 1 */
114 /* Port 0, Lane 3 */
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| H A D | armada-385-db-ap.dts | 156 /* Port 0, Lane 0 */
161 /* Port 1, Lane 0 */
166 /* Port 2, Lane 0 */
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| H A D | armada-395-gp.dts | 86 /* Port 1, Lane 0 */
92 /* Port 3, Lane 0 */
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| H A D | armada-xp-gp.dts | 189 /* Port 0, Lane 0 */
193 /* Port 2, Lane 0 */
197 /* Port 3, Lane 0 */
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| H A D | armada-375-db.dts | 46 /* Port 0, Lane 0 */
51 /* Port 1, Lane 0 */
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| H A D | armada-388-db.dts | 122 /* Port 0, Lane 0 */
126 /* Port 1, Lane 0 */
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| H A D | armada-370-mirabox.dts | 120 /* Port 0, Lane 0 */
126 /* Port 1, Lane 0 */
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| H A D | armada-xp-netgear-rn2120.dts | 199 /* Port 0, Lane 0 */
205 /* Port 0, Lane 1 */
211 /* Port 1, Lane 0 */
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| H A D | armada-xp-linksys-mamba.dts | 220 /* Port 0, Lane 0 */
226 /* Port 0, Lane 1 */
232 /* Port 0, Lane 3 */
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| H A D | armada-388-gp.dts | 219 /* Port 0, Lane 0 */
228 /* Port 1, Lane 0 */
232 /* Port 2, Lane 0 */
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| H A D | armada-370-rd.dts | 124 /* Port 0, Lane 0 */
130 /* Port 1, Lane 0 */
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanSLP.cpp | 321 for (unsigned Lane = 1, E = MultiNodeOps[0].second.size(); Lane < E; ++Lane) { in reorderMultiNodeOps() local
322 LLVM_DEBUG(dbgs() << " Finding best value for lane " << Lane << "\n"); in reorderMultiNodeOps()
327 dbgs() << *cast<VPInstruction>(Ops.second[Lane])->getUnderlyingInstr() in reorderMultiNodeOps()
329 Candidates.insert(Ops.second[Lane]); in reorderMultiNodeOps()
338 VPValue *Last = FinalOrder[Op].second[Lane - 1]; in reorderMultiNodeOps()
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| H A D | VPlan.cpp | 69 Builder.getInt32(VF.getKnownMinValue() - Lane)); in getAsRuntimeExpr()
71 return Builder.getInt32(Lane); in getAsRuntimeExpr()
233 .PerPartScalars[Def][Instance.Part][Instance.Lane.mapToCacheIndex(VF)]; in get()
239 assert(Instance.Lane.isFirstLane() && "cannot get lane > 0 for scalar"); in get()
243 Value *Lane = Instance.Lane.getAsRuntimeExpr(Builder, VF); in get() local
244 auto *Extract = Builder.CreateExtractElement(VecPart, Lane); in get()
478 for (unsigned Lane = 0, VF = State->VF.getKnownMinValue(); Lane < VF; in execute() local
479 ++Lane) { in execute()
480 State->Instance->Lane = VPLane(Lane, VPLane::Kind::First); in execute()
1131 for (unsigned Lane = 0; Lane < VF.getKnownMinValue(); ++Lane) in execute() local
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| H A D | SLPVectorizer.cpp | 925 OperandData &getData(unsigned OpIdx, unsigned Lane) { in getData() argument
926 return OpsVec[OpIdx][Lane]; in getData()
930 const OperandData &getData(unsigned OpIdx, unsigned Lane) const { in getData()
931 return OpsVec[OpIdx][Lane]; in getData()
938 for (unsigned Lane = 0, NumLanes = getNumLanes(); Lane != NumLanes; in clearUsed() local
939 ++Lane) in clearUsed()
940 OpsVec[OpIdx][Lane].IsUsed = false; in clearUsed()
944 void swap(unsigned OpIdx1, unsigned OpIdx2, unsigned Lane) { in swap() argument
945 std::swap(OpsVec[OpIdx1][Lane], OpsVec[OpIdx2][Lane]); in swap()
1186 getBestOperand(unsigned OpIdx, int Lane, int LastLane, in getBestOperand() argument
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| H A D | VPlan.h | 117 unsigned Lane;
123 VPLane(unsigned Lane, Kind LaneKind) : Lane(Lane), LaneKind(LaneKind) {} in VPLane() argument
143 return Lane; in getKnownLane()
154 bool isFirstLane() const { return Lane == 0 && LaneKind == Kind::First; } in isFirstLane()
160 assert(VF.isScalable() && Lane < VF.getKnownMinValue()); in mapToCacheIndex()
161 return VF.getKnownMinValue() + Lane; in mapToCacheIndex()
163 assert(Lane < VF.getKnownMinValue()); in mapToCacheIndex()
164 return Lane; in mapToCacheIndex()
181 VPLane Lane; member
183 VPIteration(unsigned Part, unsigned Lane,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1701 auto GetSwizzleSrcs = [](size_t I, const SDValue &Lane) { in LowerBUILD_VECTOR() argument
1703 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
1705 const SDValue &SwizzleSrc = Lane->getOperand(0); in LowerBUILD_VECTOR()
1706 const SDValue &IndexExt = Lane->getOperand(1); in LowerBUILD_VECTOR()
1725 auto GetShuffleSrc = [&](const SDValue &Lane) { in LowerBUILD_VECTOR() argument
1726 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
1728 if (!isa<ConstantSDNode>(Lane->getOperand(1).getNode())) in LowerBUILD_VECTOR()
1730 if (Lane->getOperand(0).getValueType().getVectorNumElements() > in LowerBUILD_VECTOR()
1733 return Lane->getOperand(0); in LowerBUILD_VECTOR()
1767 const SDValue &Lane = Op->getOperand(I); in LowerBUILD_VECTOR() local
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| /netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/marvell/ |
| H A D | armada-8040-mcbin.dtsi | 245 /* CPM Lane 5 - U29 */
292 /* CPS Lane 0 - J5 (Gigabit RJ45) */
302 /* CPS Lane 5 */
345 /* CPS Lane 1 - U32 */
351 /* CPS Lane 3 - U31 */
382 /* CPS Lane 2 - CON7 */
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 301 static bool matchDupFromInsertVectorElt(int Lane, MachineInstr &MI, in matchDupFromInsertVectorElt() argument
304 if (Lane != 0) in matchDupFromInsertVectorElt()
340 static bool matchDupFromBuildVector(int Lane, MachineInstr &MI, in matchDupFromBuildVector() argument
343 assert(Lane >= 0 && "Expected positive lane?"); in matchDupFromBuildVector()
350 Register Reg = BuildVecMI->getOperand(Lane + 1).getReg(); in matchDupFromBuildVector()
362 int Lane = *MaybeLane; in matchDup() local
364 if (Lane < 0) in matchDup()
365 Lane = 0; in matchDup()
366 if (matchDupFromInsertVectorElt(Lane, MI, MRI, MatchInfo)) in matchDup()
368 if (matchDupFromBuildVector(Lane, MI, MRI, MatchInfo)) in matchDup()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | LaneBitmask.h | 84 static constexpr LaneBitmask getLane(unsigned Lane) { in getLane()
85 return LaneBitmask(Type(1) << Lane); in getLane()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 445 for (int Lane = 0; Lane < LaneCount; Lane++) in createShuffleStride() local
447 Mask.push_back((i * Stride) % LaneSize + LaneSize * Lane); in createShuffleStride()
617 int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1; in group2Shuffle() local
619 IndexGroup[(Index * 3) % (VF / Lane)] = Index; in group2Shuffle()
623 for (int i = 0; i < VF / Lane; i++) { in group2Shuffle()
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| H A D | X86InstCombineIntrinsic.cpp | 492 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyX86pack() local
494 PackMask.push_back(Elt + (Lane * NumSrcEltsPerLane)); in simplifyX86pack()
496 PackMask.push_back(Elt + (Lane * NumSrcEltsPerLane) + NumSrcElts); in simplifyX86pack()
1964 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic() local
1965 unsigned LaneIdx = Lane * VWidthPerLane; in simplifyDemandedVectorEltsIntrinsic()
1969 OpDemandedElts.setBit((Lane * InnerVWidthPerLane) + Elt); in simplifyDemandedVectorEltsIntrinsic()
1979 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyDemandedVectorEltsIntrinsic() local
1980 APInt LaneElts = OpUndefElts.lshr(InnerVWidthPerLane * Lane); in simplifyDemandedVectorEltsIntrinsic()
1982 LaneElts <<= InnerVWidthPerLane * (2 * Lane + OpNum); in simplifyDemandedVectorEltsIntrinsic()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.h | 443 int Lane = -1;
446 SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
448 bool hasLane() { return Lane != -1;}
541 MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
544 : I->second.Lanes[Lane];
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | InterleavedAccessPass.cpp | 231 unsigned Lane = J * Factor + I; in isReInterleaveMask() local
232 unsigned NextLane = Lane + Factor; in isReInterleaveMask()
233 int LaneValue = Mask[Lane]; in isReInterleaveMask()
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