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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DLiveInterval.cpp67 LiveRange *LR; member in __anondae7e9140111::CalcLiveRangeUtilBase
70 CalcLiveRangeUtilBase(LiveRange *LR) : LR(LR) {} in CalcLiveRangeUtilBase() argument
94 VNInfo *VNI = ForVNI ? ForVNI : LR->getNextValue(Def, *VNInfoAllocator); in createDeadDef()
115 VNInfo *VNI = ForVNI ? ForVNI : LR->getNextValue(Def, *VNInfoAllocator); in createDeadDef()
142 return std::make_pair(nullptr, LR->isUndefIn(Undefs, StartIdx, BeforeUse)); in extendInBlock()
145 return std::make_pair(nullptr, LR->isUndefIn(Undefs, StartIdx, BeforeUse)); in extendInBlock()
147 if (LR->isUndefIn(Undefs, I->end, BeforeUse)) in extendInBlock()
288 CalcLiveRangeUtilVector(LiveRange *LR) : CalcLiveRangeUtilVectorBase(LR) {} in CalcLiveRangeUtilVector() argument
293 LiveRange::Segments &segmentsColl() { return LR->segments; } in segmentsColl()
295 void insertAtEnd(const Segment &S) { LR->segments.push_back(S); } in insertAtEnd()
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H A DLiveRangeCalc.cpp83 Updater.setDest(&I.LR); in updateFromLiveIns()
89 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, in extend() argument
99 auto EP = LR.extendInBlock(Undefs, Indexes->getMBBStartIdx(UseMBB), Use); in extend()
107 if (findReachingDefs(LR, *UseMBB, Use, PhysReg, Undefs)) in extend()
124 bool LiveRangeCalc::isDefOnEntry(LiveRange &LR, ArrayRef<SlotIndex> Undefs, in isDefOnEntry() argument
161 LiveRange::iterator UB = upper_bound(LR, End.getPrevSlot()); in isDefOnEntry()
162 if (UB != LR.begin()) { in isDefOnEntry()
169 if (LR.isUndefIn(Undefs, Seg.end, End)) in isDefOnEntry()
177 if (UndefOnEntry[N] || LR.isUndefIn(Undefs, Begin, End)) { in isDefOnEntry()
193 bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, in findReachingDefs() argument
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H A DLiveRangeUtils.h26 static void DistributeRange(LiveRangeT &LR, LiveRangeT *SplitLRs[], in DistributeRange() argument
29 typename LiveRangeT::iterator J = LR.begin(), E = LR.end(); in DistributeRange()
40 LR.segments.erase(J, E); in DistributeRange()
43 unsigned j = 0, e = LR.getNumValNums(); in DistributeRange()
47 VNInfo *VNI = LR.getValNumInfo(i); in DistributeRange()
53 LR.valnos[j++] = VNI; in DistributeRange()
56 LR.valnos.resize(j); in DistributeRange()
H A DLiveIntervals.cpp118 for (LiveRange *LR : RegUnitRanges) in releaseMemory()
119 delete LR; in releaseMemory()
160 if (LiveRange *LR = RegUnitRanges[Unit]) in print() local
161 OS << printRegUnit(Unit, TRI) << ' ' << *LR << '\n'; in print()
278 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) { in computeRegUnitRange() argument
294 LICalc->createDeadDefs(LR, Reg); in computeRegUnitRange()
313 LICalc->extendToUses(LR, Reg); in computeRegUnitRange()
320 LR.flushSegmentSet(); in computeRegUnitRange()
345 LiveRange *LR = RegUnitRanges[Unit]; in computeLiveInRegUnits() local
346 if (!LR) { in computeLiveInRegUnits()
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H A DLiveRegMatrix.cpp178 LiveIntervalUnion::Query &LiveRegMatrix::query(const LiveRange &LR, in query() argument
181 Q.init(UserTag, LR, Matrix[RegUnit]); in query()
200 [&](MCRegister Unit, const LiveRange &LR) { in checkInterference() argument
201 return query(LR, Unit).checkInterference(); in checkInterference()
214 LiveRange LR; in checkInterference() local
215 LR.addSegment(Seg); in checkInterference()
232 Q.reset(UserTag, LR, Matrix[*Units]); in checkInterference()
H A DMachineVerifier.cpp229 void report_context(const LiveRange &LR, Register VRegUnit,
235 void report_context_liverange(const LiveRange &LR) const;
244 SlotIndex UseIdx, const LiveRange &LR,
248 SlotIndex DefIdx, const LiveRange &LR,
516 void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit, in report_context() argument
518 report_context_liverange(LR); in report_context()
532 void MachineVerifier::report_context_liverange(const LiveRange &LR) const { in report_context_liverange()
533 errs() << "- liverange: " << LR << '\n'; in report_context_liverange()
2091 const LiveRange &LR, in checkLivenessAtUse() argument
2094 LiveQueryResult LRQ = LR.Query(UseIdx); in checkLivenessAtUse()
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H A DLiveIntervalCalc.cpp43 LiveRange &LR, const MachineOperand &MO) { in createDeadDef() argument
49 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
133 void LiveIntervalCalc::createDeadDefs(LiveRange &LR, Register Reg) { in createDeadDefs() argument
142 createDeadDef(*Indexes, *Alloc, LR, MO); in createDeadDefs()
145 void LiveIntervalCalc::extendToUses(LiveRange &LR, Register Reg, in extendToUses() argument
203 extend(LR, UseIdx, Reg, Undefs); in extendToUses()
H A DRegAllocFast.cpp253 void allocVirtReg(MachineInstr &MI, LiveReg &LR, Register Hint,
520 for (const LiveReg &LR : LiveVirtRegs) { in reloadAtBegin() local
521 MCPhysReg PhysReg = LR.PhysReg; in reloadAtBegin()
536 reload(MBB.begin(), LR.VirtReg, PhysReg); in reloadAtBegin()
538 reload(InsertBefore, LR.VirtReg, PhysReg); in reloadAtBegin()
675 void RegAllocFast::assignVirtToPhysReg(MachineInstr &AtMI, LiveReg &LR, in assignVirtToPhysReg() argument
677 Register VirtReg = LR.VirtReg; in assignVirtToPhysReg()
680 assert(LR.PhysReg == 0 && "Already assigned a physreg"); in assignVirtToPhysReg()
682 LR.PhysReg = PhysReg; in assignVirtToPhysReg()
729 void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, in allocVirtReg() argument
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H A DRegisterCoalescer.cpp1521 if (LiveRange *LR = LIS->getCachedRegUnit(*Units)) in reMaterializeTrivialDef() local
1522 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator()); in reMaterializeTrivialDef()
1536 if (LiveRange *LR = LIS->getCachedRegUnit(*Units)) in reMaterializeTrivialDef() local
1537 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator()); in reMaterializeTrivialDef()
2218 LiveRange &LR = LIS->getRegUnit(*UI); in joinReservedPhysReg() local
2219 LR.createDeadDef(DestRegIdx, LIS->getVNInfoAllocator()); in joinReservedPhysReg()
2303 LiveRange &LR; member in __anon3ec327350311::JoinVals
2476 JoinVals(LiveRange &LR, Register Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals() argument
2480 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask), in JoinVals()
2483 TRI(TRI), Assignments(LR.getNumValNums(), -1), in JoinVals()
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H A DLiveIntervalUnion.cpp141 if (LR->empty() || LiveUnion->empty()) { in collectInterferingVRegs()
147 LRI = LR->begin(); in collectInterferingVRegs()
152 LiveRange::const_iterator LREnd = LR->end(); in collectInterferingVRegs()
179 LRI = LR->advanceTo(LRI, LiveUnionI.start()); in collectInterferingVRegs()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/DebugInfo/GSYM/
H A DFunctionInfo.cpp158 LookupResult LR; in lookup() local
159 LR.LookupAddr = Addr; in lookup()
160 LR.FuncRange.Start = FuncAddr; in lookup()
162 LR.FuncRange.End = FuncAddr + Data.getU32(&Offset); in lookup()
173 if (LR.FuncRange.size() > 0 && !LR.FuncRange.contains(Addr)) in lookup()
181 LR.FuncName = GR.getString(NameOffset); in lookup()
225 SrcLoc.Name = LR.FuncName; in lookup()
227 LR.Locations.push_back(SrcLoc); in lookup()
228 return LR; in lookup()
238 SrcLoc.Name = LR.FuncName; in lookup()
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H A DLookupResult.cpp59 raw_ostream &llvm::gsym::operator<<(raw_ostream &OS, const LookupResult &LR) { in operator <<() argument
60 OS << HEX64(LR.LookupAddr) << ": "; in operator <<()
61 auto NumLocations = LR.Locations.size(); in operator <<()
68 OS << LR.Locations[I]; in operator <<()
H A DDwarfTransformer.cpp506 auto LR = Gsym->lookup(Addr); in verify() local
507 if (!LR) in verify()
508 return LR.takeError(); in verify()
525 NumDwarfInlineInfos != LR->Locations.size()) { in verify()
528 << LR->Locations.size() << "\n"; in verify()
535 Log << " " << LR->Locations.size() << " GSYM frames:\n"; in verify()
536 for (size_t Idx = 0, count = LR->Locations.size(); in verify()
538 const auto &gii = LR->Locations[Idx]; in verify()
547 for (size_t Idx = 0, count = LR->Locations.size(); Idx < count; in verify()
549 const auto &gii = LR->Locations[Idx]; in verify()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DLiveRangeCalc.h104 LiveRange &LR; member
118 LiveInBlock(LiveRange &LR, MachineDomTreeNode *node, SlotIndex kill) in LiveInBlock()
119 : LR(LR), DomNode(node), Kill(kill) {} in LiveInBlock()
130 bool isDefOnEntry(LiveRange &LR, ArrayRef<SlotIndex> Undefs,
150 bool findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, SlotIndex Use,
208 void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg,
244 void addLiveInBlock(LiveRange &LR, MachineDomTreeNode *DomNode,
246 LiveIn.push_back(LiveInBlock(LR, DomNode, Kill));
H A DLiveIntervals.h184 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices,
187 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices) { in extendToIndices() argument
188 extendToIndices(LR, Indices, /*Undefs=*/{}); in extendToIndices()
198 void pruneValue(LiveRange &LR, SlotIndex Kill,
245 bool isLiveInToMBB(const LiveRange &LR, in isLiveInToMBB() argument
247 return LR.liveAt(getMBBStartIdx(mbb)); in isLiveInToMBB()
250 bool isLiveOutOfMBB(const LiveRange &LR, in isLiveOutOfMBB() argument
252 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot()); in isLiveOutOfMBB()
394 LiveRange *LR = RegUnitRanges[Unit]; in getRegUnit() local
395 if (!LR) { in getRegUnit()
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H A DLiveIntervalCalc.h39 void extendToUses(LiveRange &LR, Register Reg, LaneBitmask LaneMask,
48 void createDeadDefs(LiveRange &LR, Register Reg);
54 void extendToUses(LiveRange &LR, MCRegister PhysReg) { in extendToUses() argument
55 extendToUses(LR, PhysReg, LaneBitmask::getAll()); in extendToUses()
H A DLiveIntervalUnion.h114 const LiveRange *LR = nullptr; variable
125 Query(const LiveRange &LR, const LiveIntervalUnion &LIU) in Query() argument
126 : LiveUnion(&LIU), LR(&LR) {} in Query()
133 LR = &NewLR; in reset()
143 if (UserTag == NewUserTag && LR == &NewLR && LiveUnion == &NewLiveUnion && in init()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMCallingConv.td270 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
275 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
285 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
297 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
303 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
308 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
312 : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12),
321 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
332 // For most interrupts, all registers except SP and LR are shared with
333 // user-space. We mark LR to be saved anyway, since this is what the ARM backend
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H A DThumb1FrameLowering.cpp225 case ARM::LR: in emitPrologue()
290 case ARM::LR: in emitPrologue()
466 return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) && in isCSRestore()
576 if (CSI.getReg() == ARM::LR) in needPopSpecialFixUp()
693 GPRsNoLRSP.reset(ARM::LR); in emitPopSpecialFixUp()
730 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
783 .addReg(ARM::LR, RegState::Define) in emitPopSpecialFixUp()
829 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) { in spillCalleeSavedRegisters()
831 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) { in spillCalleeSavedRegisters()
837 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) && in spillCalleeSavedRegisters()
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H A DARMFrameLowering.cpp513 case ARM::LR: in emitPrologue()
733 case ARM::LR: in emitPrologue()
1188 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt && in emitPopInst()
1237 Regs[0] = ARM::LR; in emitPopInst()
1796 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1802 SavedRegs.set(ARM::LR); in determineCalleeSaves()
1853 if (Reg == ARM::LR) in determineCalleeSaves()
1861 case ARM::LR: in determineCalleeSaves()
1884 case ARM::LR: in determineCalleeSaves()
2003 SavedRegs.set(ARM::LR); in determineCalleeSaves()
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H A DARMRegisterInfo.td94 def LR : ARMReg<14, "lr", [], ["r14"]>, DwarfRegNum<[14]>;
224 SP, LR, PC)> {
225 // Allocate LR as the first CSR since it is always saved anyway.
230 let AltOrders = [(add LR, GPR), (trunc GPR, 8),
231 (add (trunc GPR, 8), R12, LR, (shl GPR, 8))];
241 def GPRnoip : RegisterClass<"ARM", [i32], 32, (sub GPR, R12, LR)> {
242 // Allocate LR as the first CSR since it is always saved anyway.
259 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8),
260 (add (trunc GPRnopc, 8), R12, LR, (shl GPRnopc, 8))];
271 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp292 Regs.begin(), std::find(Regs.begin(), Regs.end(), AArch64::LR)); in getOrCreateFrameHelper()
297 assert(Regs[Size - 2] != AArch64::LR); in getOrCreateFrameHelper()
305 if (Regs[I - 1] == AArch64::LR) in getOrCreateFrameHelper()
319 .addReg(AArch64::LR); in getOrCreateFrameHelper()
329 .addUse(AArch64::LR) in getOrCreateFrameHelper()
340 .addReg(Type == FrameHelperType::Epilog ? AArch64::X16 : AArch64::LR); in getOrCreateFrameHelper()
365 if (std::find(Regs.begin(), Regs.end(), AArch64::LR) == Regs.end()) in shouldUseFrameHelper()
513 if (MO.getReg() == AArch64::LR) in lowerProlog()
530 emitStore(MF, MBB, MBBI, *TII, AArch64::LR, AArch64::FP, -LRIdx - 2, true); in lowerProlog()
542 emitStore(MF, MBB, MBBI, *TII, AArch64::LR, AArch64::FP, -LRIdx - 2, true); in lowerProlog()
H A DAArch64CallingConvention.td377 // requires the frame-record (LR, FP) to be at the top the callee-save area,
380 // FIXME: LR is only callee-saved in the sense that *we* preserve it and are
382 // is currently safe since BL has LR as an implicit-def and what happens after a
387 // end up saving LR as part of a call frame). Watch this space...
389 X25, X26, X27, X28, LR, FP,
397 // Win64 has unwinding codes for an (FP,LR) pair, save_fplr and save_fplr_x.
398 // We put FP before LR, so that frame lowering logic generates (FP,LR) pairs,
399 // and not (LR,FP) pairs.
401 X25, X26, X27, X28, FP, LR,
414 X25, X26, X27, X28, LR, FP,
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/netbsd-src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/
H A DPointerSubChecker.cpp44 const MemRegion *LR = LV.getAsRegion(); in checkPreStmt() local
47 if (!(LR && RR)) in checkPreStmt()
50 const MemRegion *BaseLR = LR->getBaseRegion(); in checkPreStmt()
/netbsd-src/external/gpl3/gdb/dist/sim/ppc/
H A Didecode_branch.h36 LR = new_address; \
40 update_LK, LR, cia); \

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